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Design Engineer Engineering

Location:
Bengaluru, Karnataka, India
Salary:
10000
Posted:
May 31, 2017

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T.S. SARAVANA KUMAR

No.*, Sri Nagar,

Kamaraj Avenue,

Cheran ma Nagar,

Coimbatore-35

Email ID: ac0kf1@r.postjobfree.com

Blog ID: saravanavlsi.blogspot.com

Mobile: +91-997*******

OBJECTIVE:

To work in an organization that will utilize and enhance my skill sets in the field of, CMOS IC Circuit design, Layout and ASIC, FPGA design, Verification and applications.

EDUCATIONAL QUALIFICATION:

Course

Institution

Board/

University

Year of

Completion

CGPA and

Marks %

M.E-VLSI Design

Sasurie College of Engineering, Vijayamangalam

Anna

University Chennai

2013

7.15

BE-Electronics & Communication Engineering

K.S.Rangasamy College of Technology, Tiruchengode.

Anna

University Chennai

2008

63

XII

Ashram Matriculation Higher Secondary School, Erode.

State Board

2004

67

X

Periyar Centanary Memmorial Matriculation Higher Secondary School, Trichy.

Matriculation

2002

61

ADDITIONAL QUALIFICATION:

Have completed an course on “Training Programme on IBM-MAINFRAME S/390 conducted at Software Training and Development Centre,Thiruvananthapuram” for a period of 1.5months(26-08-2008 to 20-11-2008) in MVS,JCL,VSAM,VS COBOL II,DB 2 & CICS.

Completed a course on “COBOL Programming” for a period of 21 days (30-07-2008 to 21-08-2008).

A project work was also being carried out during the course period “Credit Online Information System” designed for making financial transactions in banking sector using Mainframe. This project can also be used for making modifications to user accounts.

Completed a course in “DIPLOMA IN BASIC OPERATIONS” in Thangam Computer Center in June 2004 to July 2004

AREAS OF INTEREST:

Advanced Digital System Design

Application Specific Integrated Circuits

Testing of VLSI circuits

VLSI Design Techniques

SOFTWARE PROFICIENCY

Operating Systems : Linux, Windows Family

VLSI Programming Languages : VHDL, Verilog HDL

Layout Tools : Tanner V7, Tanner V13, PSPICE, Synopsys (VCS, Netlist )

VLSI Programming Tools : Xillinx 13.1, Xilinx 9.1

FPGA : Spartan-3E

Languages : C, C++

KNOWLEDGE AND EXPERIENCE

Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming.

Expertise in Digital Design and Advanced Verification Techniques

Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools.

Experienced with Xilinx EDK Platform.

Knowledgeable in CMOS VLSI design, Verilog RTL coding.

PROJECTS UNDERTAKEN:

ACADEMIC PROJECTS:

UG PROJECT:

Title : VLSI Implementation of Viterbi Algorithm

Duration : 6 Months

Tools Used : Xilinx 9.1, Modelsim, Spartan-3E FPGA

HDL Language : Verilog

Description : The main purpose of this project is to implement the

Prominent Viterbi algorithm used in communication systems in FPGA using VLSI (Verilog) coding, for low power applications.

PG PROJECT:

PHASE I

Title : Compact Carry Select Adder for DWT Applications

Duration : 6 Months

Tools Used : Xilinx 13.1, Modelsim

HDL Language : VHDL, Verilog

Description : The idea of this project is to reduce the area and power by connecting the Binary to Excess 1 instead of Carry ‘1’ Ripple carry adder.

PHASE II

Title : Compact Carry Select Adder for DWT Applications

Duration : 6 Months

Tools Used : Xilinx 13.1, Modelsim

HDL Language : VHDL,Verilog

Description : Here the advanced Adder is designed for to minimize the area and power by Boolean algebra and then it is applied in DWT Area, Power, Functions of the adders are compared.

COMPANY PROJECTS:

Title : Automatic car parking

Duration : 2 Months

Tools Used : Xilinx 9.1, Modelsim

HDL Language : Simulator

Description : The purpose of this project is to design a system for car parking using

Digital logic circuits.

Title : Design of Vedic Multiplier for Multiplier and Accumulator

Duration : 2 Months

Tools Used : Xilinx 13.1, Modelsim

HDL Language : VHDL,Verilog

Description : The Vedic multiplier is designed with the help of a carry select adder under the

Formula Urdhva Tiryagbhyam, and then it is applied in Multiplier and Accumulator unit.

Title : Design of 8 Transistor Full Adders

Duration : 2 Months

Tools Used : Tanner Version 7

Description : The purpose of this project is to design a full adder using TSPICE.

Title : Design of FIR Filter using Booth multiplier and SPST Adder

Duration : 2 Months

Tools Used : Xilinx 13.1, Modelsim

HDL Language : VHDL,Verilog

Description : The FIR Filter is designed with the help of a Booth Multiplier and SPST Adder.

Title : Design of IIR Filter using Wallace multiplier and SPST adder

Duration : 3 Months

Tools Used : Xilinx 13.1, Modelsim

HDL Language : VHDL,Verilog

Description : The IIR Filter is designed with the help of a Wallace Multiplier and SPST Adder.

Title : Design of Smart Arithmetic and Logic Unit

Duration : 2 Months

Tools Used : Xilinx 13.1, Modelsim

HDL Language : VHDL,Verilog

Description : The ALU is designed with the help of Adders, Shift Registers,

Binary to Excess 1 converter and decrementer.

Title : VLSI Implementation of Karatsuba Multiplier

Duration : 2 Months

Tools Used : Xilinx 9.1, Modelsim

HDL Language : VHDL, Verilog

Description : Russian Mathematician Karatsuba derived multiplication method for

polynomial multiplication. Then it is applied in Information Technology.

With the help of this method the multiplier is designed for low power applications.

Title : VLSI Implementation for CDMA NOC

Duration : 2 Months

Tools Used : Xilinx 9.1, Modelsim

HDL Language : VHDL, Verilog

Description : Communication plays a major role in our day to day life. The technology we are

Using in mobile communication is CDMA. This technology is being designed with

the help of Hardware Description Languages.

Other Projects:

Title : Credit Online Information System

Duration : 1 Month

Tools Used : IBM Mainframe S/390

Language : COBOL, SQL

Description : The main purpose of this project is to design a system for making financial

Transactions in banking sector using Mainframe. This project can also be used for

making modifications to user accounts.

PERSONAL TRAINTS

Flexible and willingness to accept new challenges

Desire to learn and update emerging technologies

Ability to work as a group and individually

Excellent communication skills

Enthusiasm to know new technologies

ADDITIONAL INFORMATION

Design and development of various HDL modules using Xilinx Spartan-3E FPGA board.

Xilinx FPGA board programming using ISE.

Design HDL modules using Xilinx IP cores.

EXPERIENCE:

Company Name: SPIRO Technologies

Designation: VLSI Trainer, Seminars in VLSI, Classes in Verilog & VHDL, Business Development Officer

Duration: 11 months

Company Name: MAHINDRA Next Wealth

Designation: Trainee

Duration: 6 months

College: Sasurie College of Engineering

Designation: Lecturer

Duration: 6 months

Current Job:

Company Name: Crisp Systems India Private Ltd

Designation: VLSI Trainer, Seminars in VLSI, Classes in Verilog & VHDL,

ACHIEVEMENTS:

Bagged second prize in mini-project title is “Automatic car parking” competition held at K.S.Rangasamy College of Technology, Tiruchengode.

Exbited a model entitled “Anti Deleting File” in K.S.Rangasamy College of Technology, Tiruchengode for Tamil Nadu State School Students.

Presented a paper in “Compact Carry Select Adder for DWT Applications” national and international conferences held at Institute of Road and Transport Technology and Sasurie College of Engineering, Vijamangalam.

WORK SHOP:

Attended a workshop in “SYNOPSYS – VLSI Design Tool” in Kongu Engineering College, Perundurai.

Attended a workshop in “SOLID STATE MODELLING AND SIMULATION” in KPR Institute of Engineering and Technology, Arasur.

Attended a workshop in “Hands on Training in NS2” in Sasurie College of Engineering, Vijayamangalam.

JOURNALS:

Publication of the journal in International Journal of Advances in Engineering & Technology under the topic of “Area Minimization of Carry Select Adder using Boolean algebra”

EXTRACURICULLAR ACTIVITES:

Participated in various singing and oratorical competitions at school level.

Represented my school team in Volleyball competitions at Zonal level competitions.

Participate in cricket tournament in school level.

PERSONAL PROFILE:

Name : T.S.SARAVANA KUMAR

Date of Birth : 12.04.1987

Age : 29

Blood group : B+

Mother’s Name : S. Kalarani (Late)

Father’s Name : T.S. Subramanian (Late)

Present address : No.5, Sri Nagar, Kamaraj Avenue, Cheran Ma Nagar, Coimbatore-35, Tamil Nadu, INDIA

Permanent address : 61/8, CSI colony, Sanarmedu, Erode-638 002, Tamil Nadu, INDIA

Religion : Hindu

Nationality : Indian

Languages Known : Tamil, English

Hobbies : Reading books, Gardening, Playing Chess

I hereby declare that all the details furnished above are true and correct to the best of my knowledge.

Place :

Date :

(SARAVANA KUMAR T S)



Contact this candidate