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VIYA VIJAYAN

Aloth House, SMP Colony Road, Kodamkulangara, Tripunithura P.O, Kochi, Kerala, Pin: 682301 RTL/FPGA Design Engineer

LINKEDIN

www.linkedin.com/in/viya-vijayan

E-MAIL

ac0jqv@r.postjobfree.com /

ac0jqv@r.postjobfree.com

TELEPHONE

999-***-**** /

949-***-****

To build a career as an VLSI front end Design Engineer in a reputed organization, wherein, I can add significant values to the organization by combining my theoretical knowledge and practical experience to deliver original concepts in the field of FPGA based system or in the field of ASIC design and development. SUMMARY OF CREDENTIALS

• M.TECH in VLSI and Embedded Systems Engineering with 2.5 Year experience in RTL coding, research and development of custom IPs and custom FPGA board design.

• Expertise in FPGA design/RTL design flow with fluency in Verilog HDL coding

• Good Experience in integration and implementation of RTL modules and on-board testing

• Hand on experience in EDA tools like Xilinx ISE, EDK, VIVADO, QuestaSim and ModelSim

• Experience of using real time debugging tools like Xilinx Chip Scope Pro and Logic analyser

• Hand of experience in custom FPGA board and expansion modules (ADC, HDMI, VGA etc

• Good knowledge of digital design, concept of System Verilog based verification and Universal Verification Methodology(UVM).

• Team player with good communication skill and documentation skill. TECHNICAL SKILL SET

PROFESSIONAL QUALIFICATIONS

Qualification Institution Duration

ASIC Design and Verification Course Maven Silicon, Bangalore April 2015- August 2015 M.Tech

(VLSI&ES)

MG University, Kerala 2012-2014

B.Tech (ECE) MG University, Kerala 2008-2012

HDL : Verilog

HVL : System Verilog

Verification Methodology : Universal Verification Methodology (UVM) FPGA Design Tools : ISE, EDK, SDK, VIVADO, QuestaSim, ModelSim Debugging Tool : Chipscope Pro analyser, Logic Analyzer Protocols : AXI4 (stream, Lite, Full), AHB, APB, SPI, I2C, UART, PCIe Viya Vi jayan viya.a loth@gma i l . com

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PROFESSIONAL EXPERIENCE

Associate Engineer April 2016 – present

(VLSI R& D) Bangalore, Cochin

Numato systems Pvt. Ltd.

Numato system Provides quality embedded system products, FPGA based product and services to customer all over the world.

Responsibilities:

Design and bring up of FPGA and non-FPGA based products

RTL design, synthesis, simulation and related tasks for IP and test applications

Manage product planning, hardware design, document, prototyping and plan for manufacturing readiness

Documentation for internal and external use

Projects undertaken:

Design and implementation of DAQ IP (Running): DAP IP core is a soft IP core which is used for data acquisition purpose. This IP can have connected to the AMBA AXI. Project responsibilities included Created detailed architecture including all submodules and signals, created feasibility report and design document of minimal design core, designed minimal function Core using Verilog and tested through simulation, on board testing and modifying Core to meet full-fledged design. Tool and HDL used: Verilog, VIVADO, Chipscope, XILINX ISE

Design of FPGA custom development board (Running): Spartan 6 FPGA with USB 3 compliant development board. Project responsibilities included manage product planning, hardware design includes power requirements, IO mapping, pin mapping and documentation and research on available USB 3 ICs in the market

Design and implementation of AXI-UART IP(Completed): AXI- UART (Universal Asynchronous Receiver / Transmitter) IP connects to the AMBA AXI and provides the controller interface for asynchronous serial data transfer. Project responsibilities included created detailed architecture including all submodules and signals, designed Core using Verilog, tested and debugged on board using numato’s Skoll (FPGA Development board) and logic analyser and documentation of user manual, design document and package it as a soft IP Core. Tool and HDL used: Verilog, VIVADO, Chipscope, XILINX ISE, Logic Analyzer

Design and implementation of AXI-IIC IP(Completed): AXI- IIC IP connects to the AMBA AXI and provides two wire simple serial interface. This soft IP core is a single IIC master. Project responsibilities included created detailed architecture including all submodules and signals, designed core using Verilog, tested and debugged on board using numato’s Skoll (FPGA Development board) and logic analyser and documentation of user manual, design document and package it as a soft IP Core. Tool and HDL used: Verilog, VIVADO, Chipscope, XILINX ISE, Logic Analyzer

PCIe-FPGA communication (Completed): PCIe-FPGA communication include read and write task between host and FPGA via PCIe. Project responsibilities included modified Xilinx PCIe IP core for custom use, documentation of PCIe-FPGA communication project and tested using Host Linux system, Galatea (FPGA development board) and LED jig. Tools and domain/platform used: Verilog, ISE, XPS and Linux System Viya Vi jayan viya.a loth@gma i l . com

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Project Intern Sep 2015 – Dec 2015

(Design & Verification) Bangalore

Maven Silicon Softech. Pvt. Ltd.

Maven Silicon is a unique VLSI Training Centre based out of Bengaluru, offering advanced VLSI Design and Verification courses. Provides industry level internship for skilled graduates. Responsibilities:

RTL Design using Verilog HDL and simulation

Verify design using latest verification methodologies like System Verilog based verification and Universal Verification Methodology(UVM) based verification. Projects undertaken:

AXI UVC - AMBA AXI4 Protocol Verification: The AMBA AXI protocol is targeted at high-performance, high- frequency system and includes several features that make it suitable for a high-speed submicron interconnects. AXI UVC is a configurable UVM based verification IP. Project responsibilities included architected the class based verification environment in UVM and verified the protocol with single master single slave environment by connecting maters and slave back to back. Tools And domain used: System Verilog, UVM, QuestaSim

Design of Physical Coding Sublayer (PCS): Physical Coding Sublayer(PCS) interface is the Gigabit Media Independent Media(GMII) that provides a uniform interface to the reconciliation sublayer for all 1000 Mb/s PHY implementation. PCS is working at 125 MHZ. Project responsibilities included designed RTL using Verilog and verified the design in Verilog environment. Tools And domain used: Verilog, ISE

AHB2APB Bridge IP Core Verification: The AHB to APB Bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses. Project responsibilities included architected the class based verification environment in UVM, verified the RTL module with single master and single slave and generated functional and code coverage for the RTL verification sign-off. Tools And domain used: System Verilog, UVM, QuestaSim

Design & Verification of Router 1x3: Router is an OSI layer 3 routing device and project aimed at developing the RTL using Verilog HDL and verify the same RTL using UVM Methodology. Project responsibilities included designed RTL using Verilog and developed architecture of verification environment using SV & UVM. Tools And domain used: System Verilog, UVM, QuestaSim, ISE, Verilog Project Trainee (VLSI) July 2013 – Aug 2014

Network system and technologies Pvt. Ltd (NeST) Trivandrum NeST Technologies is a highly diversified Engineering Services organization with the experience and passion to apply innovative technologies to market application. Responsibilities:

Research on new efficient CCL algorithm

Develop/modify CCL algorithm

MATLAB scripting without use of MATLAB functions

RTL design of proposed architecture

Viya Vi jayan viya.a loth@gma i l . com

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Projects undertaken:

Design & Implementation of run length based connected component labelling system: Connected component labelling (CCL) system is used to find the connected components in a video or image. CCL is a major step in ADAS system. Project responsibilities included developed a CCL algorithm for efficient FPGA implementation, designed a MATLAB script without using inbuilt MATLAB functions and designed RTL using Verilog. Tools and domain used: Verilog, ISE, MATLAB PERSONAL DETAILS

Nationality : Indian

DOB : 06/03/1991

Marital Status : Single

Blood Group : B -ve

Passport Number : M7809480

Hobbies : Glass embossing, reading selected books, Playing with children Achievements : Selected as the chairperson of the college student’s union, Selected as the college ladies Hostel student’s mentor, 2011 gate qualified,

Coordinator of ECE branch tech fest,

Individual sports champion in schooldays

DECLARATION

This is to certify that all the information provided above are true to the best of my knowledge. Date: 30/05/2017 Viya Vijayan

Place: Kochi, Kerala

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