Pierre Dermy

**** ******** ****** **

Reno, NV **506

775-***-**** / 530-***-**** (M)

ac0bc5@r.postjobfree.com

Experience and capabilities

Integrated Circuit (IC), Printed Circuit Board (PCB) and Electronics Design Engineer with over 35 years experience in high-performance RF, analog and digital electronics, optimization for high-speed or low-power, system testability and reliability. Track record of successful analog and mixed-signal IC designs: AC/DC voltage converters, point-of-load (PoL) electronic power distribution and management, RF wireless transceivers, multi-Gbps wireline I/O (HSTL, LVCMOS, LVDS, PECL, BTL), HV I/O buffers, signal integrity analysis, SerDes, ADC, video DAC, PLL, analog micropower IC, microprocessors, FPGA prototypes and embedded MCU applications, IC packages (CSP and MCM), fine-line PCB, signal integrity, EMI-RFI and ESD protection.

CAED tools: Tanner EDA L-Edit Pro, T-SPICE Pro, Mathcad, Ansoft Designer, LabView, Sonnet, Electronics Workbench, Icarus Verilog, Alliance VLSI Tools, Altium Designer, Altera Quartus II, Aldec HDL Express, IAR Embedded Workbench, IAR KickStart, SolidWorks

Programming languages: UNIX C&B-Shell, PERL, Verilog, C Project Management tools: MS Project, MS Office Suite Consulting services and IP development

RFID Tags, ADC: pipelined, flash and SD, DAC, PLL, DC power converters, charge pumps and V/I regulators, RF transceivers, SRAM.

Consulting on I/O buffers and pad rings (PECL, LVDS, HSTL, LVCMOS, PCI, BTL), ESD and latch-up protection circuits, backplane and PCB signal integrity analysis, IC and POL power distribution, noise immunity, BGA and flip-chip packaging, frequency synthesis, clock distribution networks, circuit timing and testability. Page 1 of 4

List of projects from 2000 to present

Most recent project: (Company Confidential) from July, 15 2013 until December 31, 2016. Consulting, IC design and technology development in CMOS 30/20 nm technology for Digital, and Analog Mixed-Signals applications, integrating a new type of Si devices to produce better integration density than a FinFET-based 16 nm CMOS technology. Design of VLSI Digital, SRAM, CAM and Analog circuit cells to show the feasibility. VLSI CAE/D method and development plans. Device physics and VLSI fabrication plan with CMOS Si IC foundry, including Si die processing steps as well as photomask and circuit design rules. Product and IP development plan for Internet-of-Things, RF radios and communication processors for 5G, sensor interface circuits, communication network processor based on open source computing library, and cybersecurity hardware engine. International patent application, with most claims approved: WO2016057973-A1. Other projects:

Consulting on encapsulated power supplies and drivers of LED lamps, circuit simulation of electrothermal effects. System architecture, design partitioning: HW-SW, PCB and IC partition, MCU and development tools. Definition of DFTM flow and test benches. Solutions and impact of 3-D integration and packaging. Consulting on the technologies and markets for Passive Optical Network components: FTTH/X deployment, integration of fiberoptic connectivity into PC’s and Si dice. Design of wireless electrical power converter and transceiver for medical implant. Synchronous SRAM in 0.18mm CMOS, circuit design, IC mask layout, memory block

(128X12 to 8192X64 bits) assembler (Unix B-Shell script and L-Edit UPI macro). Design of a micropower RF transponder for a battery-operated RFID Tag in 0.50mm CMOS process and with MOSFET’s operating in weak inversion. Design of a bipolar OpAmp for EMI application ( VCC 6 V to 30 V, ICC < 15 mA, cap. load up to 20 nF, DC gain 80 dB, UGB 80 MHz, SR 350 V/μs with CL 50 pF, DC output swing 80 % of VCC ) with power down control.

Redesign and IC mask layout of 5V-tolerant I/O Buffers and ESD protection circuit of a Crystal/RC Oscillator Pad, in a CMOS 0.35mm technology. Design in SOI CMOS 0.13mm technology of programmable voltage generators for VLSI applications and SRAM with high dynamic load (500mA peak and 500ps transients), combining coarse and fine voltage regulation loops. Design in SOI CMOS 0.13mm technology of HSTL and LVCMOS I/O with analog and digital calibration.

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Design in SOI CMOS 0.13mm technology of a high-current negative voltage generator

(-2.0V 2.0mA) with smart power regulation: US Patent 6,756,838. Novel ESD Protection Circuit for a SOI CMOS 0.13mm technology: US Patent 7,187,530. Design of a video analog front end in a CMOS 0.25mm technology. Pipelined ADC’s with 8/10bit ENOB, 175/30MSps sampling rate, digital error calibration, programmable input clamp, synchronization pulse detection and HSYNC/VSYNC separation, PLL and frequency synthesizer (input 15-110kHz output 10-175MHz, jitter of 10ps at 10MHz and 200ps at 175MHz).

Architecture and first-pass design in a CMOS 0.18mm technology of a SerDes CDR and LVDS parallel bus interface (16bit wide data and 1 clock) with a data transfer rate of 1.56GBytes per second.

Design in a BiCMOS 0.80mm technology of a micropower undervoltage detector for battery monitoring in cellular phones and portable equipment (LMS33460). Architecture and first-pass design of a 12bit ADC and data acquisition IC in a silicon BiCMOS 0.50mm technology. Sampling rate 1GSps, ENOB 11bit, dual port FIFO buffer, open/closed loop auto calibration and BIST modes.

List of client companies and all projects prior to 2000, provided upon request Direct/W4 employers

T-RAM, Inc. - San Jose, CA

nDSP Corp., Campbell - San Jose, CA

National Semiconductor Corp., Analog Products – Sunnyvale and Grass Valley, CA Performance Semiconductor Corp.- Sunnyvale, CA

IMP, Inc. - San Jose, CA

Data General Corp. Semiconductor Division - Sunnyvale, CA Fairchild Semiconductor Corp. R&D Labs - Palo Alto, CA Education

Diplome d'Ingenieur (BSEE-MSEE)

Ecole Superieure d'Ingenieurs en Electronique et Electrotechnique Paris, France - 1980.

MSEE, with Research Assistanship

University of Cincinnati, Ohio - 1981.

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Research work

* GaAs device modeling, digital and RF analog circuits.

* GaAsInP semiconductor laser.

* Data acquisition and electronic control circuits.

* Si analog IC design and processing, semiconductor device manufacturing.

* Fabrication of MOS tunnel diodes and solar cells.

* MSEE Thesis: "MOS Interface Trapped Charge Characterization Using The AC Conductance Technique"

Membership

Institute of Electrical and Electronic Engineers (IEEE) since 1979. Technology Alliance Bridge: www.tabridge.com, Silicon Valley, since 1996 Chinese American Semiconductor Professional Association: www.caspa.com Military service

Reserve Officer in the French Air Force (active duty 1976-77). Hobbies

Alpine skiing, mountain hiking, canoeing, fishing.

Auburn Ski Club (www.auburnskiclub.org), Alpine Ski Coach.

Member of Professional Ski Instructors of America (www.thesnowpros.org)

Boy Scouts of America, Golden Empire Council (www.gec-bsa.org) Nevada City, California Troop 24, Assistant Scoutmaster. Page 4 of 4

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