Verilog, VHDL, Digital Logic Design, Assembly Language, Microprocessor

ASHOKCHAKRAVARTHI MUPPA

E-Mail:

*****************.*****@*****.***

Contact no: +91-905*******.

Objective

Seeking a challenging and growth oriented position to

utilize my skills and abilities while being resourceful and to update

myself with the latest technologies to work for the growth of an

organization.

Educational Profile

Course

Languages: : Verilog HDL, VHDL.

Synthesis Tools : Xilinx ISE 13.4.

Simulator Tools: Modelsim, Isim.

Key Skills : Sound Knowledge in Digital Logic Design, Stick

Design & Layout

Design of NMOS, PMOS, and CMOS circuits,

Assembly

Language Programming of 8086,

Microprocessor.

Projects

Project 2:

Title: Radix-8 Booth Encoded Modulo 2n-1 Multiplier

Language: Verilog HDL

Tools: Xilinx ISE 13.4

Description: The encryption and decryption of the public key cryptographic

(PKC) algorithms are performed by repeated modulo multiplications.

The soft multiples are generated using the bitwise

circular-left- shift operation and bitwise inversion. The hard multiple is

generated using small word length ripple carry adders (RCAs) operating in

parallel. The Multiples are represented in the partially-redundant form.

To avoid having many long strings of ones in the carry

of negative hard multiple an appropriate bias added. To negate the effect

of the bias the compensation constant (CC) is added.

The Modulo 2n-1 multiplier is usually the non-critical

data path among all modulo multipliers, this timing slack can be exploited

to reduce the system area and power consumption.

Project 1:

Title: Design and implementation of 16450 UART

Language: Verilog HDL

Tools: Xilinx ISE 10.1

Description: UART is a familiar protocol in vlsi industry. The one I

designed is the basic 16450 which can transmit and receive 8 bit data along

with start and stop bits. Dual rank synchronizer is used to avoid meta

stability in the receiver. This project involves design specifications, RTL

design, test bench coding and verification and Implementation of design on

Xilinx Spartan-3E device.

Personal Profile

Name : Ashokchakravarthi Muppa

Father's Name : M. Omkaram

Date of Birth : 19-08-1987

Gender : Male

Marital Status : Single

Languages Known : English & Telugu

Hobbies : Listening to Music, Watching Movies, Playing Cricket

Preferred Contact : Mail/Phone

Address : Koppole, Ongole (Mandal), Prakasam(District), Pin:

523287.

Date:

Place: Ashokchakravarthi M

Contact this candidate