Design Power

ROHIT K. RAMNANI

****, * ****. *****, #****, Tempe, AZ 85281 480-***-**** ********@***.*** http://www.linkedin.com/in/rramnani

Objective Looking for challenging career opportunities in the field of Analog, RF or Mixed-Signal

VLSI Circuit Design.

Education

8/11 – Present Arizona State University Tempe, AZ

(Expected 5/13) Master of Science, Electrical Engineering

Cumulative GPA: 3.65/4.0.

Completed Courses: Analog Integrated Circuits, Advanced Analog

Integrated Circuits, Microwave Circuit Design, Nyquist rate ADCs, Communication

Transceiver Circuit Design, VLSI Design, and Digital Systems & Circuits.

8/07 – 6/11 Mumbai,

Mumbai University

Bachelor of Engineering, Electronics & Telecomm. India

Cumulative GPA: 3.9/4.0, Awarded with Merit scholarship.

Skills Software: Agilent ADS, MATLAB, Cadence Virtuoso Schematic and Layout Editor,

Spectre/AMS/APS Simulator.

Hardware: CRO, Function Generator, DMM, Spectrum Analyzer.

Operating Systems: Windows, Linux.

Industrial Experience

5/12 – 1/13 Intel Corporation Santa Clara,

Intern, High Speed Input-Output team (HSIO) CA

HSIO interface circuits for data transfer

The objective of the team was to design a full semi-custom IC for serial

communication – USB, SATA, PCIe for a low power tablet.

Roles

- Designed a 24 MHz flash comparator and verified it for its reliability and

statistical variations (Monte Carlo). Verified high speed clock monitor port

circuits, resistor compensation port circuits, ADCs for MC/MPP, aging,

EOS/ERC violations in Cadence. Used Cadence in full fledge throughout

internship- RVmeasC, MPP/Nova/MC, ERC/EOS, Relxpert Aging, and

Scarlet.

- Worked with the tool DAs to solve critical violations/reports.

- Participated actively in design reviews and giving feedback to the circuit

designers for functional simulations and other critical issues.

- Supported the team for many critical tasks in a very important phase, before

tape out; documenting and presenting the work assigned.

Projects Rail to Rail Amplifier Design:

Designed a 2 stage rail to rail amplifier with parallel connected PMOS and NMOS differential

amplifier using CMOS 0.25 um process. The ICMR was = 0 – 3V. With a load cap of 1pF, a

gain of 40 dB with unity gain frequency of 80 MHz was successfully achieved. The beta

multiplier biasing circuitry was designed with minimum power dissipation. Supply voltage=

3V. The total power dissipated was achieved to be 1 mW to satisfy the specification.

PSRR+ was 59 dB, with PSRR-= 51 dB. The amplifier was also configured in unity gain

configuration to measure output swing= 0.3 Vpp, with input swing = 0.3 Vpp.

(Arizona St Univ.)

Design of CMOS beta multiplier based current reference current mirrors:

Designed 3 current mirrors – pmos cascoded, pmos and nmos both cascoded, regulated gate

cascode; rectified the reference current and voltage generated for c onstant trans conductance

over temperature variation from – 20 C to -85 C. Successfully attained a % matching of 0.01

% between the two branch currents of current mirror. The basic principle followed was to

control the gm of transistor by the external res istor R, to control the current in the 2 mirror

branches. The other transistors were slaved by this transistor . (Arizona St Univ.)

Design Of A Symmetric Operational Trans conductance Amplifier (OTA):

Designed a cascode OTA with common – source output buffer stage. Gain of 55 dB, Gain-

Bandwidth product = 55 MHz with load cap of 1 pF, phase margin = 60 degre es, CMRR = 55

dB, Slew rate =6.8V/us with input step of 10 V/us, HD3 of 45dB, PSRR of 40 dB, and an input

referred noise = 10 nV/sqHz. The quiescent power dissipation was 1.25 mW, with a 1 Vpp

swing at the output if connected in unity follower configuration. (Arizona St Univ.)

Design of a PMOS input folded cascode amplifier:

Designed a single ended PMOS input folded cascode amplifier with a class AB output

buffer circuit. Successfully achieved 100 dB open loop gain, with load cap of 200 pF, gain

bandwidth product = 57 MHz, gain margin = 31 dB, phase margin = 68 degrees, PSRR of

84 dB, CMRR = 6.4 kdB, input referred thermal noise = 14 nV/sqHz, HD3 of 60 dB, Slew

rate of 6.95 V/us, output swing = 1 Vpp. (Arizona St Univ.)

Design of Engine controller for a 12 -cylinder 6-speed car:

Worked with and led a team of 7 members to design th e architecture, sub -blocks and layout

and parasitic extraction for the complete chip.

• Power was optimized by using full static logic in all the blocks.

• Worked on the integral control blocks of the chip which takes inputs (road slope, wind

etc.), to adjust RPM and gear to maintain the speed constant, from the interface blocks and

The loads - cylinders and gears were emulated as capacitive and resistive loads.

(Arizona St Univ.)

Design of 4-section coupled line bandpass filter

Designed a 0.5 dB equal ripple response band pass filter and laid out in ADS momentum

tool on a Rogers RO4350B substrate. The center frequency of filter had 2.45 GHz,

Bandwidth = 10%. The filter had an insertion loss of -3 dB within the pass band.

(Arizona St Univ.)

Design of a 90 degree Schiffman phase shifter

Designed a coupled line section phase shifter and simulated in ADS. The phase shifter had a

BW of 2.1 GHz for a phase variation of 90 +/ - 3 degrees. (Arizona St Univ.)

Design of a Bandpass filter using micro strip lines

Designed a 0.5 dB equal ripple band pass filter using short circuited stub resonators for a

cutoff frequency = 3GHz, BW=20%; laid out the filter in micro strip on a Rogers substrate.

The filter had an insertion loss of +/ - 3 dB in the pass band. (Arizona St Univ.)

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