Design Engineer
Resume:
Pflugerville, Texas *****
Home: 512-***-**** Cell: 512-***-****
SUMMARY
Expert in Place and Route, Static Timing Analysis, Design Rules Checking
and Layout vs Schematic checking . I have worked on full chip designs as
well as delivering IP for a chip design. As the lead Extraction support
person for IBM my responsibilities included: writing technology files,
characterizing technology files for parasitic extraction. Proven ability to
learn new methodologies and new tools and adapt them to meet design
requirements. Strong communication and organizational skills. Experience in
digital circuit design, IO circuit design, development of ASIC design flows
from RTL to GDSII. Lab work to correlate simulated models to actual
hardware.
DESIGN TOOLS AND LANGAUGES
Spice simulation, Cadence Virtuoso Editor, Star-RC, DRC, LVS, LPE, ERC,
ICC, Encounter, Finale, PrimeTime, PTPX, Apache, Red Hawk and Calibre DRV.
Experienced in coding perl, tcl, ksh and Cadence's skill. Worked with:
Solars, Linux (Red Hat), AIX, Windows NT, Windows 7, Excel, Powerpoint,
Outlook, and Lotus Notes. I have some C and Java experience.
EXPERIENCE:
8/2010-12/2012 AMD Corporation (IP Design), Austin, Texas
Unified North Bridge lead responsible for partitioning of logic, floor
planning the logical partitions into physical elements of design, place and
route, clocking, scan, timing, power and delivering GDSII that is Design
Rules clean to the chip on schedule.
. Expert in CVS revision control process to check out/in of RTL changes and
code updates for ASIC Design tools.
. Partitioning of RTL into logic blocks to achieve critical timing
improvement of 15%.
. Place, route and buffering of logic blocks to meet a timing target of
designs up to 2.5GHZ.
. Implement Clock mesh and power mesh at top block and push down to
physical blocks.
. Implement gated clocks to achieve critical slack and clock skew targets.
. Implement scan rings to achieve a clock target of 400 MHZ.
. Responsible for addressing noise, EM, IR, and timing issues before
delivering hierarchical blocks to chip team.
. Deliver Design Rule clean designs based on the TSCM 28nm process.
. Owned setting goals and planning resources to insure aggressive schedules
are met.
5/2006-7/2010 IBM Corporation (Design Automation), Austin, Texas
Position: Design and support for tools doing extraction, Static Timing
Analysis and Simultaneous Switching.
Application lead for 3D global extraction and Simultaneous Switching. Work
with design team to insure accurate parasitic calculations and
simultaneous switching based on scheduled requirements..
. Created tech files for parasitic extraction and simultaneous switching
tools for 32nm and 45nm IBM process. Insure accuracy of tech files using
Spice simulators. Verify design implementation in excess of 5GHZ.
. Contributed to CAD teams efforts in reducing the extraction run times by
70%.
. Expert at tracing Power/Ground shorts for the chip team at the time when
LVS does not give adequate information for locating actual shorts..
. Supported CAD tools in the execution of Static Timing Analysis,
extraction and noise analysis for both RLM and chip level designs. This
included writing flows to support the setup and execution of these tools
. Worked with team to implement a streamed line interactive flow to do PD
on the (RLM)Route-Level-Modules for the current IBM tool set. This included
writing Perl as well as TCL to implement functions to the bridge the gap
between vendor tools and internal tools.
. Worked with development team to create a flow that would calculate
parasitics for stacked chips. This include how to calculate the coupling
for the vertical interconnect through one chip to the attached chip.
. Worked extensively on converting native GDSII tools over to OpenAccess
based tools resulting in run time improvements
. Also have written Cadence SKILL based functions and menus.
9/1998-5/2006 IBM Corporation (STG divison), Austin, Texas
Position: Microprocessor Design
. Key contributor to tracing Power/Ground shorts for the chip team at the
time when LVS did not give adequate info for locating actual shorts..
. Was timing closure lead for the L2 design of the IBM Cell Processor. This
require floor planning and buffering buses over the L2 cache. Negotiating
with macro designers to establish assertion requirements.
. Key contributor to the implementation of Timing windows for noise impact
on delay. Worked with CAD teams to better derive the actual effects of edge
rates.
. Work with team to implement a streamed line. Interactive flow to do PD on
the Route-Level-Modules for the current IBM tool set. This include writing
Perl as well as TCL to implement functions to the bridge the gap between
vendor tools and internal tools.
. Floor planning, defining pin placement and assessing required
interconnect typologies to achieve timing goals.
. Implemented a flow to defined interconnect models for early Static Timing
Analysis. Also created tcl to driver custom router to achieve actual
interconnect routes.
6/1978-9/1998 IBM Corporation (s/390 division) Kingston and
Poughkeepsie, New York
Position: Design and Packaging Engineer
ASIC chip and logic card designs for Networking products
. Implemented balanced clock trees with a slew target of 3% for 4 chips.
. Simulated card interconnect between chips to insure signal integrity.
. Created mechanical drawings in support of product release.
. Lead rules coder for tech file and rules used by Cadence Card design
system.
. Lab debug of cards/chips, implement engineering changes required for
system test.
. Wrote and implemented card test plan used at card assembly. Include
debugging and fixing test patterns.
EDUCATION:
AAS in Electrical Engineering
SUNY at Morrisville NY, 1973-1975
Marist College 1986-1994
Courses taken: Introduction to C, Calculus, Personal Computer
Concepts
Patent 201******** on A METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT
DESIGN.
Collaborated on two (2) papers: designing the cell processor and designing
the gigabit processor.
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