Design Project

SANTHOSH KESHAVARAPU Hyderabad, A.P

Mobile:+918*********

ABV-Indian Institute of Information Technology

and

Email: ********.******@*****.***

Management

India.

OBJECTIVE

Seeking challenging position where I can effectively utilize my education

knowledge in the area of VLSI. Learn new skills and to continually enhance

the development of my professional skills.

EDUCATION

Year Degree/Certificate Institute/University CGPA

Indian Institute of Information 8.44/10

2012 M.Tech Technology and

Management, Gwalior (M.P.)

2010 B.Tech JNTU Hyderabad 83.64 %

2006 Class 12th Board of Intermediate Education, 94.0 %

AP

2003 Class 10th Board of secondary Education, AP 89.66 %

ACADEMIC PROJECTS

M.Tech Thesis Design of Stability Enhanced Low Voltage 8T SRAM cell

Title: for Video Applications

. Broad Area: Memory Design( Static RAM Design)

. Aim: To propose a new mechanism which enhance the read and write

margins of low voltage SRAM cell by which the stability is to be

enhanced and apply it to video applications.

. Description: The analysis of SRAM read/write margin is essential for

low-power SRAMs. The 8T SRAM cell has the challenge with respect to

write Noise margin. So In this a new assist technique is proposed

which enhance the stability(Read and write margin) of SRAM cell. This

Stability is important parameter for image quality in video

applications. As the stability of SRAM is enhanced this new SRAM cell

can be applied to MPEG-4 video applications.

. Tools used: Tanner(S Edit, T Spice, L Edit, LVS), 90nm TSMC

technology.

M.Tech Academic Project Title: Analysis of PPN Based 10T SRAM cell with low

leakage for Ultra low power applications.

. . Broad Area: Low power Memory Design

. Aim: To Design and analyze a 10T SRAM cell with low leakage and operate

in subthreshold operation for Ultra low power applications.

. Description: In this a PPN based 10T SRAM cell is analyzed with

respect to leakage and dynamic power and static Noise margin and also

with delay. It is observed that this 10T SRAM cell has low leakage and

resilient subthreshold operation for ultra low power applications.

. Tools used: Tanner(S Edit, T Spice, L Edit, LVS), 90nm TSMC

technology.

B.Tech Academic Project Title: Reconfigurable Real Time signal

capturing.

. . Broad Area: RTL Design

. Aim: To capture and analyze the baseband and IF signals of communication

system and implementing the necessary modules in VHDL.

. Description: In this project a technique for capturing and analyzing

the baseband and IF signals of communication system are implemented

with configurable UART Interface. VHDL is used for the implementation

of necessary modules for block memory, condition checker, triggering

logic and UART interface..

. Tools used: ModelSim Xilinx Edition (MXE) will be used for functional

simulation and verification. Xilinx ISE is used for synthesis and

performance analysis.

PUBLICATIONS

. Santhosh Keshavarapu, Saumya Jain, Manisha Pattanaik, "A New Assist

Technique to Enhance the Read and Write Margins of Low Voltage SRAM

cell", IEEE, International Symposium on Electronic System Design

(ISED)

2012 (Accepted).

. Saumya Jain, Santhosh Keshavarapu, Manisha Pattanaik, Balwinder Raj,

"A 10-T SRAM Bitcell With Inbuilt Charge

Sharing For Dynamic Power Reduction", IEEE, International conference

on Advances in Technology and Engineering(ICATE), 2013. (Accepted)

ACADEMIC HONORS

> Scored 97 percentile in GATE 2010 from Electronics & communication

branch.

> Secured 1st position in class 12th with an aggregate of 94.0%.

> Received 'The Academic Excellence Award' all throughout four years of

B.Tech.

> Won first prize in Technical Quiz conducted at National level which

was held as 'ANURAG VISTA' in 2009.

AREA OF INTERESTS

. Memory Design (Static RAM)

. RTL Design using HDLs

. CMOS Digital Design

SKILL SET

Operating System: MS Windows 98/XP/Vista

Programming Languages: C,C++, VHDL,Verilog

Tools: Tanner, Silvaco IC CAD, HSPICE, PSICE, Xilinx,FPGA

CO-CURRICULAR ACTIVITIES

> Participated in various cultural and technical fest held at college

level.

> VHDL Training in Globe Arena, Hyderabad.

> Member of Hostel activity committee.

> An active member of the Literacy Project of school.

PERSONAL DETAILS

Name Santhosh Keshavarapu

Father's Name Sudhakara chary

Marital Status Single

Nationality Indian

Hobbies Reading Magazines

Permanent Address H.NO.13-138, Lingagiri Road, Huzurnagar,

Nalgonda(Dist)

Andhra Pradesh, Pin-508204

Phone No +918*********

Date of Birth 26-01-1988

DECLARATION

I hereby declare that the above mentioned information is correct up to my

knowledge and I bear the responsibility for the correctness of the above

mentioned particulars.

Place: Hyderabad K. Santhosh

Date:

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