Design Engineer Electrical Engineering

Jingxu Li **** Veteran Ave. #***.Los Angeles.CA **024 408-***-**** ***********@*.****.***

EDUCATION

Bachelor of Science in Electrical Engineering

• University of California Los Angeles June 2013

• De Anza College August 2010

SKILLS

• Experienced in processing analog and digital circuit using PSPICE CADENCE or LOGISIM

• Proficient in handling lab equipment: Transistor Curve Tracer, Spectrum Analyzer, Oscilloscope, Signal Generator Soldering Iron Microscope, MyDAQ, Lab Brick

• Familiar with Visual C++ and MATLAB

PROFESSIONAL EXPERIENCES

Richtek Technology Corporation, San Jose, CA June to September 2012

Design Engineer Intern

• Designed and verified DC to DC converter and transient control function (mixed CMOS circuit) for load box

• Designed and verified internal power system and other mixed Bipolar circuit for Fuse Zapper

• Physical implementation (layout) of circuits and de-bug designs using lab equipment

• Burn internal metals of IC modules using microscope, and test separately

IEEE design Lab, UCLA Sep 2012 to March 2013

Design Engineer and Team Leader

• Designed and simulated Linear Regulator (LDO) given reference voltage and power system for MicroMouse according to provided ICD

• Controlled motor driver H-Bridge by 8-bit AVR processor microcontroller and recorded speed by quadrature encoder

• Implemented an algorithm for MicroMouse on Arduino platform, and programming to get navigation routine

• Applied IR sensor to plan path, PID control to reduce error, and controlled motor speed by the duty of PWM

PROJECTS

CE Amplifier Design (Analog Circuit) UCLA

• Designed a single stage CE amplifier circuit given specific gain and power dissipation using PSPICE

• Designed a CE-CC amplifier circuit given a limited gain, and increased the gain by adding current source

• Simulated the CE amplifier, and applied a transient analysis using pulse voltage instead of analog voltage.

Clock Distribution Network Design (Digital Circuit Transistor Level) UCLA

• Constructed a schematic composed of the clock tree (inverter chain) that implements the desired clock distribution network using CADENCE

• Sized the inverter chain and simulated the circuit to check if performance targets meet transition time and skew objectives

• Layout the circuit and performed design rule and layout versus schematic checks

Arithmetic Logic Unit Design (Digital Circuit Module and Logical Level) UCLA

• Edited two basic modules Const (constant signals) and Logic (bitwise logic operations) for the four-bit inputs

• Implemented Arithmetic adder by designing the fullAdder module to calculate the sum and carry for a pair of input bits and one carry-in bit.

• Implemented Comparator by designing the compBit modules to compare two input bits with regard to the results of the previous bit, and complete the ALU work

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