LVS DEBUG SOLUTIONS LLC
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639 Caliente Dr, Apt 2
Sunnyvale, CA 94085
ph: 408-***-****
****@***-*****-*********.***
backpage - Arya's resume
ARYA RAYCHAUDHURI
(nickname: Mithu)
E_mail: ***********@*****.***
Phone: 408-***-**** (cell)
639 Caliente DR, #2
Sunnyvale, CA 94085 USA
Experience/Interest:
FullChip Tapeout Expertise in Calibre Physical Design Verification, ruledecks development using Calibre SVRF, complex LVS/DRC debug on IcStation, Virtuoso, CalibreDesignRev platforms. Special purpose application code development using SVRF (with run-time TVF switching), CalibreDRV-TCL and Perl for automated physical design generation and modification for Shorts Isolation, Yield-sensitive structures mapping, Stress Vias and Via opportunities identification and addition, fullchip Power Planes generation, metallization/actives changes for DFM and chip integration (putting sub-blocks together, editing sub-blocks). Layout extraction with Calibre XRC. Addressing run-time and hierarchy issues. Atoptech-based block level PD work, Primetime reports parsing for setup/hold time fixing. Perl recursives for SPICE Analysis. PerlShell based modification of verilog/cdl netlists (for v2lvs) to help multiple voltage domains LVS, Perl based PDV flow development. Hercules LVS. [With deep earlier experience in Device Physics/Modeling, Process/Device Simulation, and Spice Modeling]
WORK STATUS: Naturalized US citizen, OCI India
September 2012 credit scores: eq-809,ex-825,tx-801
EXPERIENCE:
11/2011-present Proprietor, LVS DEBUG SOLUTIONS
Projects Done so far:
First multi-chip module tapeout LVS with Calibre, metals respins for a single chip, hspice based dynamic/static leakage power calculation for a digital sub-block, via densitity adjustment with calibre.
Developing (in progress) the code snippets page indicating new LVS ideas and fundamentally interesting new shell/perl/svrf/tvf/tcl/spice codelets
12/2007- 10/2011 Fulltime - part time - Fulltime again: Fastrack Design, Senior Staff Design Engineer (Calibre PDV) - PDV Manager
Atoptech-based block level PD work, Primetime reports parsing for setup/hold time fixing. Perl recursives for spice analysis tree extraction with net trace.
Worked on FullChip Tapeout for various customers doing designs in TSMC90, Chartered90, TSMC65, TSMC130, TSMC180, TSMC250, Fujitsu65, Fujitsu90, TSMC40, Toshiba40nm processes. Mainly in Calibre, one tapeout in Hercules.
Electronic Design paper on using Calibre for Layout Generation and Modification http://electronicdesign.com/article/embedded/correct-by-construction-layout-generation-and-modi
Electronic Design Paper on DRC/ERC data splitting algorithm http://electronicdesign.com/article/eda/Programmed-Splitting-Of-Full-Chip-Calibre-DRC-ERC-Errors-Into-Sub-Block-Space.aspx
EETimes Paper on Perl-Calibre based Junction Vias Deficiency Checker/Adder http://www.eetimes.com/electrical-engineers/education-training/tech-papers/4130134/Chip-IR-Drop-Reduction-Through-Automated-Via-Checking-and-Addition
Developed specialized SVRF code, Perl/Shell/tcl scripts for problem solving. DFM work with Cadence LPA, CCP. Spice simulations.
12/2010 12/2011 (moonlighting consultant): Jasper DisplayCalibreDRV-TCL, Shell, Perl based GDS design conversion from TSMC to Fujitsu design rules, various shell/perl flows for Calibre
5/2009- 6/2009 (full-time contract): Uniquify Consultant
1/2007 - 11/2007: Ikanos Communications, Fremont, CA Contractor/Full-time EngineerHelping resolve tapeout PDV issues in Calibre DRC/LVS/ERC
6/2004 - 3/2006: Advanced Micro Devices, CA MTStaff Design EngineerCalibre SVRF, Calibre-DRV TCL, Perl-based Complex Layout Generation (such as fullchip powerplanes), layout ModificationDevelopment of Calibre techfiles for complex fullchip layout debugs - such as pinpointed signal to non-signals, power-ground shorts isolation (using DRC method), metals pitch profiling and mapping to predict possible metal-bridging locations on chip (using LVS method).Development of Perl-Calibre-TCL solutions for fullchip DRC debug - filtering DRC errors for sub-blocks interfaces, locating/modifying cells instances with specific properties, fullchip DRC runtimes profiler to isolate slow checks
6/2002 - 10/2003: Sun Microsystems Sunnyvale/CA Physical Design Verification LeadLeading physical design verification efforts through incorporating new flows and procedures for complex verification tasks. Such as multiple supply voltages design rules checking through domain separation. Efficient and effective redundant (metal stress related) Vias checking. Via opportunities/ERC techfile. Enhancement of the display of metal density results. Calibre-based extraction of the flipchip pads maps. DRC regression test cases generation and automated running. DRC/LVS debug of fullchip and sub-blocks using Vituoso and Calibre.
6/1997 - 6/2002: Rockwell/Conexant Newport Beach, CA Manager, Layout and Technology AnalysisMain Developer of Physical Verification and Extraction decks for post-layout verification and extraction, based on Mentor s Calibre/xCalibre SVRF. Many companies in Irvine area use those decks.Supported designs in CMOS, BiCMOS, Bipolar, Analog, Mixed-Signal, Silicon-Germanium, and GaAs technologies. Design rules review.Managed a small group of 4 engineers working in physical verification/extraction areas.
8/1996 - 5/1997: PMC Sierra Inc. Vancouver, B.C. Layout Verification EngineerDeveloping layout verification code for CMOS designs on Mentor Platform, after training with Mentor Graphics.
1/1996 - 7/1996: Glenayre R&D Inc. Vancouver, B.C. Signal Processing EngineerModeling of r.f. power amplifiers from system perspective, using Matlab.
9/1991 - 12/1995: Simon Fraser University Burnaby, B.C. Graduate Research AssistantDeveloped a virtual factory-type simulation environment using SUPREM4 and MEDICI on the UNIX using SHELL and C programs.Analysed the early mode of the hot carrier degradation using floating gate, charge pumping, and transconductance techniques, as well as simulation.Designed a new static memory scheme using resonant tunneling diodes. Worked with HP-VEE and AURORA.
5/1993 - 9/1994: Northern Telecom Ltd. Nepean, Ontario Co-op Research StudentInvestigated hot-carrier reliability, and impact ionization-induced substrate and gate currents for sub-micron NMOS devices using extensive measurements and simulation. Coauthored two company technical reports in the TCAD area.
10/1987 - 7/1991: Indian Institute of Technology (IIT) Kanpur, UP Senior Research EngineerAnalyzed the impact of ion-beam damage on thin oxide MOS structures using admittance spectroscopy and ellipsometry. Modelled the electrical features of such damage. Multiple research publications.Developed software for data acquisition and data analysis using HP semiconductor test system and other HP and Keithley equipments. The software was written in HP-BASIC.
10/1983 - 10/1987: Semiconductor Complex Ltd. Mohali, Punjab Member, Technology Development TeamDesigned and developed a process evaluation test chip for a 3-micron CMOS process developed in-house. Formulated complete topological design rules for all mask levels of 3-micron CMOS layouts corresponding to the above-mentioned process.Developed improved techniques for short channel MOSFET parameter extraction and modeling (published SCL s first IEEE paper http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=2436&contentType=Journals+%26+Magazines - early thoughts on surface potential based modeling).Designed and developed an electrostatic-discharge (ESD) protection networks test chip for comparison of various options.
EDUCATION 6/1996: Simon Fraser University Canada-B.C.-Burnaby
Ph.D. : Thesis title: Modeling and simulation of saturating hot electron degradation in LDD NMOSFETs - from early mode to late mode. [125+ citations for the constituent papers, theis nominated for Douglas Colton medal]
http://summit.sfu.ca/system/files/iritems1/6998/b18000745.pdf7/1983: Jadavpur University (Electronics & Telecom. Dept.) India- West Bengal-Calcutta
M.S. : Specialization in electronic devices, thesis on switching speed of a novel MOSFET inverter. Coursework Percentage of Marks: 72.7.
B.S. : Electronics & Telecommunication Eng. GPA 3.64
ADDITIONAL INFORMATION: Academic HonorsAwarded National Scholarship, India in 1976.Canadian Commonwealth Scholarship, 1991.Graduate Fellowship, 1992, Simon Fraser U.President s Research Stipend, 1993, Simon Fraser U.Dean s Scholarship, 1994, Simon Fraser U.Hector J. MacLeod Award, 1995,IEEE, Vancouver Section.publications have been well cited (>125)in international journals .I have been asked to review publications for IEEE (EDS).
Selected Publications (Look in scholar.google.com for more)
[1] A. Raychaudhuri, W.S. Kwan, M.J. Deen, and M.I.H. King, Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs, IEEE Trans. on Electron Devices, ED-43, 1114-1122 (1996).
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=502423&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D502423
[2] A. Raychaudhuri, M.J. Deen, M.I.H. King, and J.Kolk, Finding the Asymmetric Parasitic Source and Drain Resistances from the A.C. Conductances of a Single MOS Transistor, Solid-State Electronics, 39, 909-913 (1996).
http://www.sciencedirect.com/science/article/pii/0038110195002693
[3] A. Raychaudhuri and M.J. Deen, New static storage scheme for analogue signals using four-state resonant-tunneling devices, Electronics Letters, 29, 1435--1437 (1993).
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=252479&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D252479
[4] A. Raychaudhuri, Z. X. Yan, M. J. Deen, and A. C. Seabaugh, Hysteresis in resonant-tunneling-diode-based multiple-peak driver device for multivalued SRAM cells: analysis, simulation, and experimental results, Canadian Journal of Physics, 70, 993-1000 (1992).
http://www.nrcresearchpress.com/doi/abs/10.1139/p92-159
[5] A. Raychaudhuri, S. Chatterjee, S. Ashok, and S. Kar, Ion-dosage- dependent room-temperature hysteresis in MOS structures with thin oxides, IEEE Trans. on Electron Devices, ED-38, 316-322 (1991).
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=69912&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel1%2F16%2F2451%2F00069912.pdf%3Farnumber%3D69912
[6] Arya Raychaudhuri, New product idea: Adio-visual newspapers, published on soc.culture.bengali, March 22-26, 2009
https://groups.google.com/group/soc.culture.bengali/browse_thread/thread/353b9fcde1e29deb/fdaa182f82ba1c13?hl=en&lnk=gst&q=information+watch#fdaa182f82ba1c13
Copyright 2011 LVS DEBUG SOLUTIONS. All rights reserved.
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639 Caliente Dr, Apt 2
Sunnyvale, CA 94085
ph: 408-***-****
****@***-*****-*********.***
Copyright 2011 LVS DEBUG SOLUTIONS. All rights reserved.