Electrical Engineer Software

Location:

Camden, NJ

Posted:

December 10, 2012

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Mark Bersalona

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Professional Experience Summary

Electrical Engineer with extensive and increasingly responsible

assignments in hardware and software design, implementation and test.

Expertise in the following:

Digital hardware design/implementation/test (9 years)

Electronic circuit card assemblies (CCAs) including:

microprocessors; memories; field-programmable gate arrays (FPGAs)

and programmable logic devices (PLDs); interface and networking

ICs; digital logic and voltage

regulators

Interfaces for serial (RS-232, I2C, HOTLink) and Ethernet

communications

Design verification and test; hardware/software integration;

troubleshooting to component level

Tools for schematic capture and board layout: Mentor Graphics

Design Architect, Layout

Documentation: design descriptions; interface documents; user

manuals; test procedures

Software design/coding/test (12 years)

High-level languages: MS Visual Basic; C; FORTRAN; Pascal;

BASIC; PL/I; dBASE; VAX DCL

Embedded real-time operating systems: VxWorks; Green Hills

velOSity

Low-level assembly code: Motorola 68HC11; Intel 8051; MOS

6502; UYK-20/44

Unit-level test; hardware/software integration; design

verification

Documentation: design descriptions; pseudocode design

language; user manuals; test procedures

Experience

1988 - 2010

L-3 Communications, Communication Systems - East, Camden,

(formerly GE Aerospace, Government

Communications Systems Department;

formerly Martin

Marietta Communications Systems;

formerly Lockheed Martin Communication Systems)

Electrical Engineer

in-line network encryptor (INE) (11/2007 6/2010)

Tested and debugged KG-245X Optical Interface Card (OIC)

10 Gbps CCAs. Hardware troubleshoot KG-245X units and

Management, Data and OIC CCAs

Provided engineering support for KG-245X production

INEs (11/2005 11/2007)

Developed interface adapters for KG-245A 1 Gbps

INE: Ethernet copper (10/100/1000Base-T)

and optical interfaces (1000Base-SX/-LX).

Adapted KG-245A electrical design for KG-240A 100 Mbps

INE (10/100Base-T and 100Base-FX); adapted KG-240A electrical

design for proposed 1 Gbps INE.

Designed small CCAs: KG-245A Reverse Polarity Protection

CCA; adapter card for KG-240A FPGA test connectors; adapter

card for KG-245A RJ-45 connector.

Supported ECAD efforts for KG-240A Encryptor CCA and

KG-245A interface flex layout/routing.

Debugged first set of KG-240A CCAs. Thermal confidence

testing of KG-240A and 1 Gbps variant.

Conducted miscellaneous hardware development and

integration.

Provided engineering support for KG-245A and KG-240A

production.

Lead-free Initiative (9 11/2005)

Designed CCA to evaluate lead and lead-free hardware components

with L-3 CS-E manufacturing processes and equipment, including

failure detection.

KG-3X Cryptographic Modernization Initiative, Phase I (4-9/2005)

Partitioned KGV-335 hardware prototype into separate

CCAs.

Designed Crypto CCA from schematic capture to component

layout for handoff to ECAD routing.

secure terminal (4/2000-4/2005)

Designed, developed and tested embedded software task to interface

Conexant SmartMDP/SmartDAA PSTN modem chipset:

Offhook/onhook/ring detection; V.8, V.32, V.34 modem negotiations;

compatibility with allied PSTN network standards.

Resolved software trouble reports in OMNI embedded

software.

Direct Dial (3/1998-4/2000)

Created new simulators to run on Sun workstations for

development of Direct Dial (DD) gateway software. Developed DD

gateway host task for processing digital messages sent/received

over satellite link. Modified networking software for use in DD

gateway.

IMSE Dismounted Network Key Generator (DNKG) (10/1997-3/1998)

Modified software written in MS Visual Basic and C++ for DNKG

(host is a ruggedized laptop) to address and close problem reports.

Responsible for software builds.

IMSE Common Cryptographic Module (CCM) (5-10/1997)

Designed and implemented box-specific software written in

C for Intel 80C251 processor for Trunk Encryption Device

(TED) and Secure Voice Order Wire

Completed TED hardware-software integration

Developed software utilities written in MS Visual Basic

for IMSE: Key Loader Simulator and IMSE Uploader

Advanced Message-Oriented Data Security Module (AMODSM) (3/1996-5/1997)

Designed and implemented hardware and software for the

AMODSM Functional Tester: a PC ISA card with software written

in MS Visual Basic.

Wrote, verified and ran the Acceptance Test Plan and

related Tester scripts. Wrote and dry-ran Design Verification

Tester scripts. Assisted writing Crypto Verification Tester

scripts.

Baseband Switch proposal support (3/1996)

Designed test fixture for and conducted testing on ON-143/KG-84

Variable Interface Delay, the results of which were needed to

support the Baseband Switch proposal effort.

Space Station Video Baseband Signal Processor (VBSP) (3/1995-3/1996)

Ran hardware acceptance tests for

VBSP design verification model and for VBSP

Special Test Equipment.

Surveyed available comb filters for VBSP redesign and

conducted electrical, thermal and vibration tests on a

prototype repackaged comb filter for the VBSP flight model.

Designed hardware test fixtures and wrote test procedures

for VBSP flight model.

LMD/KP,

Key Processor (KP)

Software (10/1994-3/1995)

Wrote detailed test procedures for KP software, which involved

single-stepping through code via debugger to determine proper

breakpoint locations and register values while running on

target hardware. Target processor was Motorola 68030.

Series 7000 satellite (7-10/1994)

Martin Marietta Astro Space Division, East Windsor,

Modified box-level test procedures and prepared Test Readiness

Review packages for Series 7000 communications satellite.

High-Rate Space Recorder (HRSR) (12/1992-7/1994)

Designed and developed a comprehensive parts database to

be used on HRSR. Developed exclusive access feature to allow

single-user, MS-DOS version of Alpha Four database manager to

be used safely on networked Sun workstations.

Designed, implemented and debugged 4M/16M DRAM hardware

test fixture, which consists of Xilinx field-programmable

gate array (FPGA) and TTL logic and optional error

information download to a PC via DMA interface. Modified the

download software to include graphical error mapping for TI

4M SuperShrink die. DRAM test fixture was used for

single-event upset/single-event latchup radiation tests on

DRAM die at Brookhaven National Laboratories, Long Island,

NY.

Designed, implemented and debugged HRSR DCU/DMU interface

hardware prototype, used to demonstrate validity of HRSR

DCU/DMU interface using realistic cabling, drivers and

operating speed. Conducted tests under varying speed,

voltages and temperatures, and published results.

Performed initial hardware design of HRSR bench test

equipment.

High-Rate Tape Recorder (HRTR) (2-12/1992)

Modified Xilinx FPGA designs from Small Format IR&D for use

in HRTR. Design, simulation, autorouting, and resimulation were

performed in MS-DOS environment (Schema III, PC-Silos) and

Mentor Graphics/Sun environment (NetEd, Quicksim, Exemplar).

LMD/KP Hardware (6/1991-1/1992)

Wrote Intel 8051 assembly code to test and debug Red I/O

interface cards at wirewrap breadboard stage. Assisted

debugging Red I/O interface card. Generated wirewrap netlists

for LMD/KP boards using dataPLACE+ layout software. Debugged

dataPLACE VALID-to-Mentor conversion software.

LMD/KP Multi-Purpose Test Equipment (MPTE) (2-6/1991)

Demonstrated interprocessor communications among VME-based

single-board computers running VxWorks real-time operating

system, Sun workstations and an HP controller with FUSION

networking software, to be used during software development for

Multi-Purpose Test Equipment.

IRR Software

Maintenance (1-6/1988; 3-9/1989; 6/1990-2/1991)

Resolved software problems of the Integrated Radio Room

for Trident submarine. Verified software fixes of other

engineers. Target computer was UYK-20/44.

Developed support software for IRR software engineers.

Modified existing support software. Target was DEC VAX; the

utilities were written in DEC FORTRAN, PL/I, Pascal, DCL.

1-6/1987

Streets Department, City of Philadelphia

Engineering Intern

Designed and developed RECYCLE database in dBASE III+ (MS-DOS PC)

to track costs and participation in a test municipal recycling

program.

Education

MSEE, Drexel University, 12/1993, GPA 3.625/4.0

BSEE, Drexel University, magna cum laude, 6/1990, GPA 3.753/4.0

Awards

Communications Systems President's Award, 2000 (for work on

Direct Dial)

Communications Systems President's Award, 1997 (for AMODSM

Functional Tester)

Space Station Contributor of the Month, 3/1996

Other Qualifications

U.S. Government SECRET security clearance

Webmaster, Bersalona.com and SawyersCreek.org

Attended several in-house Continuing Education Program technical

classes

GE Edison Engineering/Advanced Course in Engineering program

Graduate specialization in digital signal processing and

communications

Deans List, Drexel University - 5 years

Co-authored "A Computer Evaluation of the Philadelphia Curbside

Recycling Program." Presented 3 May 1988. (ASME)

National Merit Scholar; John McKee Scholarship

Served as Librarian, Philadelphia Amiga Users Group,

5/1990-4/1991.

Notes

Email: ****@*********.***

Updated 2010.06.15

reserved.

URI: http://Bersalona.com

Comments? Queries? ****@*********.***

Modified: 2010.06.15 19:58

Be at Peace...

reserved.

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