Electrical Engineer Design

KEYUR PAYAK

(**** Montecito Avenue, Apt#*, Mountain View, CA 94043 ( Cell: 435-***-****

( Email: *****.*****@***.***

OBJECTIVE

Obtain an Electrical engineer position with Analog Circuit design emphasis

in a Semiconductor firm.

SUMMARY

Strong experience in designing CMOS amplifiers, memory circuits, data

converters, error correcting circuits and digital integrated circuits.

Familiarity with signal integrity issues for High Speed I/O.

EDUCATION

( M.S Electrical Engineering, Utah State University GPA: 3.87/4

Graduation Date: May 2010

( B.E, Electronics and Communication, RGTU, India %: 71 %

Graduation Date: May 2007

TECHNICAL SKILLS

( Analog Design Tools: Cadence Virtuoso, Spectre, Cadence Concept, Spectre,

OrCad, ADS, Verilog AMS.

( Digital Design Tools: Verilog, Cadence RC, SoC Encounter, Xilinx ISE,

Modelsim, SimVision.

( Testing Skills: Boundary Scan, JTAG, DFT, DRC, LVS, Oscilloscopes,

Network Analysers.

( Programming: C, C++, Verilog, Verilog-AMS, Matlab, SPICE, Perl, shell

scripting, SKILL, Java, C#, HTML.

( Other: Microsoft Windows OS, Linux, Mac OSX, Wireshark, Symantec Ghost,

Microsoft Office suite.

PROJECTS AND COURSES

Memory ( SRAM with Integrated Soft Error Control Decoder: Design and layout of a

Circuits 64X64 SRAM with an auxiliary soft error control decoder for increasing

noise immunity of differential bit lines. (0.6um, Spectre)

( DRAM System level implementation: Transistor level design of DRAM system

architecture and addressing timing issues between driver, pre-charge,

sense-amplifier and latch circuits. (0.6um, Spectre)

Data ( 4-bit. 1.5 bit/stage Pipelined ADC: Design of a pipelined ADC along with

Converter designing an ideal Verilog-AMS model which was used for

s verification/reference purposes. (0.6um, Spectre, Verilog-AMS).

( 8-bit Flash ADC: Study and Simulation of an 8-bit Flash ADC with a

Look-Up-Table (LUT) for digital correction that eliminated the requirement

of having high precision comparators. (0.6um, Spectre, Matlab)

Amplifier ( High Gain Operational Trans-conductance Amplifier: Design and layout of

s a telescopic OTA with 85dB gain, 150MHz bandwidth and 45 Phase Margin.

(0.6um, Spectre)

( Two-stage Op-amp with Common Mode Feedback: Design of a 60dB, 300 MHz

two stage Op-amp (Differential Amp followed by a Common Source stage) for

a Sample and Hold circuit (0.6um, Spectre).

Verilog ( 4-stage DLX Pipelined Processor: Verilog RTL simulation, synthesis and

full scan of a 4-stage DLX pipelined processor. Handled data and control

hazards stalls. (Verilog, Modelsim, Cadence RC).

( 8-bit Accumulator based Microprocessor: Design of a stored-program

microprocessor dealing with synchronization issues between RAM, Control

Unit and the ALU. (Verilog, Xilinx, Modelsim)

C/C++ ( LDPC Stochastic Iterative Decoder: C simulation of a (2000,1000) LDPC

Iterative Decoder employed in communication receivers using the novel

stochastic computation algorithm.

( OSI Model: Designed OSI model stack bottom up. Entire project was done

in C++. All 7 layers of this model were designed in phases and were

verified for functionality.

Courses ( Microelectronics, Analog VLSI-I, Analog VLSI-II, Digital VLSI, CMOS VLSI

Design, Mixed Signal VLSI, Semiconductor Devices and Physics, Computer

Networks

EXPERIENCE

( Research Assistant, ECE Department, USU: CMOS Implementation of an

iterative decoder using stochastic computation. This novel approach allows

the decoder to be less complex and power efficient. (0.18um, Spectre,

Matlab).

( Teaching Assistant, ECE Department, USU: Served as a TA for several VLSI

courses: Microelectronics-I, Microelectronics-II, Science of Sound.

( Computer Systems Administrator, Mathematics and Statistics Department:

Maintaining departmental servers and computer labs and interacting with USU

Information Technology Desk for security and software licensing.

PUBLICATIONS

( Keyur Payak and Chris Winstead, "Power and Complexity in Stochastic

Decoders", in 7th Annual International Analog Decoding Workshop, Logan,

Utah.

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