Chau Nguyen

eMail: abmkof@r.postjobfree.com

San Jose, CA Phone: 408-***-****

Physical Design Engineer

Qualifications

Over 10 years of successful experience in designing mixed signal IC.

Areas of expertise includes ASIC design, Physical Design, Flow and

Methodology

. Successful engineered top and block level physical integration of

hierarchical design, and flat design from netlist, floor-plan,

place and route, LVS/DRC to tape out

. Hands-on experience in Static Timing Analysis, Power Net Analysis,

IR drop, Signal Integrity with Synopsys IC Complier (ICC), Astro,

Conformal LEC, Hercules

. Developed scripts to manage signal integrity, to prevent coupling

noise on high frequency signals (2GHz), power routes with Cadence

Chip Assemble Router (CCAR). Effectively working on floor plan

with Virtuoso_XL, Assura

. Familiar with physical synthesis of Magma Talus Vortex

. Knowledge of EDA tools for circuit design, simulation, Unix, Awk,

Perl, SKILL, Pcell

. Comprehensive knowledge of design verification, CMOS device

characterization

. Knowledge of efficient back-end design flow, strong problem

solving, pressure handling abilities

. Ability to manage priorities and work flow. Strong interpersonal

skills, versatility, flexibility. Proven ability to handle

multiple projects and meet deadlines

Professional Experience

Integrated Device Technology/ Integrated Circuit Systems, San Jose, CA

2005-2009

(Integrated Device Technology Inc. acquired Integrated Circuit Systems Inc

on 09/19/05)

Sr. Design Engineer/Physical Designer

. Successful engineered full chip and block integration, Place and

Route with Cadence Layout_XL, power bus, clock tree analysis,

voltage drop analysis for Clock Generator, PCI-Express, Zero Delay

devices CMOS technology

. Developed power templates, Cadence CCAR scripts, to automate, and

to update ECO's, scripts to maintain layout design flow and to

effectively shorten the tape out time to 50%

. Created SKILL files for many blocks to eliminate repetitive work

in layout, resulting in faster layout time

. Wrote numerous Astro, CCAR scripts to auto-route blocks, signals,

signals matching, wires shielding and power templates

. Interfaced with tool vendors to migrated and modified the library

from Charter foundry to IDT in-house fab

. Provided 10 ECO/running-change tape-outs in a month to meet

aggressive schedule

. Extensive experienced in modifying analog blocks/mixed-signal

blocks, PLL, XTAL, Bias, Charge Pump, Regulator, SRAM, ROM

. Performed failure analysis on silicon on bench

Integrated Circuit Systems 1997-

2005

Sr. Design Engineer

. Supported new chip and block development including P&R to tape-out

and ECO's after initial tape-out

. Responsible for new chip design feasibility, bonding, Verilog

functional, timing verification, and critical signals optimizing,

for PC motherboard clock of 4-PLL and 5-PLL device

. Performed Mixed-signal Hspice simulation for skew matching on

critical paths

. Performed parasitic extraction, Voltage Storm power analysis,

layout review/supervision

. Implemented IBIS run set and responsible for IBIS library. Wrote

Awk script for auto-creation IBIS files which resulted in shorter

response time to customers

. Performed new products debugging on bench

Product Engineer

1995-1997

. Responsible for coordinating testing board, characterization, and

releasing product for Frequency Timing Generator device,

ICS9154/9155, ICS9161

. Responsible for design validation

. Implemented automation test/characterization using LabView software

to facilitate the interface between PC and bench equipment

. Developed Excel macros to auto-generate reports from

characterization data

. Worked with design, and test engineering on design changes and spec

reviews, studied process variations

. Wrote Product Specifications, Product Verification flow

. Supported manufacturing products, including sustaining, yield

improvement and cost reduction

Quality and Reliability Engineer 1992-

1995

. Performed physical and electrical analysis on failures from

internal and external customers; identified defects and issued

corrective actions

. Conducted liquid crystal test, detected hot spots, probed defective

ICs

. Performed continuation and reliability engineering, ESD, latch-up

tests

. Assisted in implementation of test plan to eliminate error between

rejected parts with tested good parts

Education: BS Electrical Engineering San Jose State University

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