Engineer Design

CAREER OBJECTIVE: Seeking a position in Digital, ASIC/FPGA design,

verification and/or testing, DSP, Image processing and video codec's.

EXPERIENCE SUMMARY

* Having 4.5 years of direct work experience in RTL design (Verilog, VHDL),

verification, synthesis and timing verification, DSP, image processing IP

design on FPGA and video codec's.

* And 1.5 years of project experience in M. Tech project.

* Having expertise in SoC integration, Spyglass linting and power

management checks.

* Having experience in Digital signal processing.

* Having expertise in video standard development on FPGA (SECAM standard).

* Having knowledge in image processing algorithms and hands on experience

in image processing IP design like Image edge detection and vehicle

tracking etc. on FPGA.

* Worked on Fixed point mathematics and developed RTL.

* Having expertise in Digital filter design.

* Having good experience in error detection and correction codes in

communication and implemented Forward Error Correction (FEC) on FPGA for

Digital Video Broadcasting standard DVB-s2 standard.

* Hands on experience in development of error correction codes like RS,

BCH and LDPC codes

* Worked on FPGA design in which the already existing codes for PAL in ABEL

are converted into VHDL coding and implemented using Xilinx tool.

* Worked on complete implementation of IP 's like Image compression

standard JPEG, FFT, DCT, Quantization, BCH Encoder, BCH

Decoder, Image processing IP's like Edge detection and corner detection

on FPGA with successful architectures and testing successfully on board.

* Experience in real time Digital logic design and verification, VHDL

design

and synthesis.

* Worked on circuit simulation and modelling.

* Having experience in Fixed point mathematics.

* Worked on Pico-Express (Synfora Inc) tool on evaluation and IP design

which converts 'C' language to RTL.

* Worked on memories (SRAM, DRAM) and their circuit analysis in KT tools.

IT EXPOSURE

Programming Languages C, C++, VHDL, Verilog, ABEL, PERL, TCL and

Sequel.

Assembly Language

Programming 8085, 8086, 8051 and DSP processor

Packages TMS320F2xx.

Simulation Tools

FPGA Tools MATLAB, P-SPICE, Orcad.

ModelSim, ISE

Asic Tools Xilinx Synthesis ISE Tools, Altera

Operating Systems Quartus II, Synplify

Pro, Pico-Express etc.

Design Compiler, Prime Time, 0in, SpyGlas,

LEC, Autogen etc.

Windows -NT, MS-DOS, Linux

ACADEMIC CREDENTIALS

Degree University/Institute Year of Marks

Passing

M.Tech(EE IIT Bombay 2006 9.0/10.0 CGPI

Department)

B. Tech Andhra University 2004 86.81%

(E.E.E.)

Diploma in State Board of Technical 2000 81.77%

EEE Education and Training

SSC Board of Secondary 1997 84.00%

Education

Work Experience

. Worked as an Electronic System Designer in KLA-Tencor Corp. India

Private Ltd, Chennai from August 1st 2006 to May 15th 2007.

. Woprked in Softjin Technologies as Senior Design Engineer, Bangalore

from May15th 2007 to October 15th, 2010.

. Currently working in Mirafra software Technologies Pvt Ltd as Senior

Design Engineer (Deployed to Texas Instruments).

Key Projects

Project Done ASIC tool Expossure: In Qualcomm, I worked on

different environments and tools. Having hands on

experience on ASIC tools like Design Compiler, 0in,

Prime Time, SpyGlass etc.

Currently working in Texas Instruments on deputation.

In Texas Instruments majorly working on SoC

integration, SpyGlass linting, Logical Equivalence

checking (LEC) and Power Management check using

SpyGlass.

Development of radix- 2 FFT IP: In this project,

complete implementation and testing of radix-2 Fast

Fourier Transform (FFT) on FPGA using verilog is

being done. For high throughput ping-pong

architecture has been implemented. The design gives

high performance with low area occupation. This IP

core has been thoroughly tested functionally using

available C code.

Client : Achronix.

Duration: 2 months.

Role : Design Engineer.

Deliverables for this project are:-

1. Verilog RTL source code

2. Test benches

3. Synthesis and Simulation scripts.

4. Detailed user documentation, including RTL source

code documentation.

Development of DCT core on FPGA: In this Discrete

Cosine Transform (DCT) is designed and synthesized on

FPGA using verilog. Design architecture is such that

it gives best performance with lower area

requirement. Design has been thoroughly tested

functionally with references like MATLAB and C code.

Client : Achronix.

Duration: 2 months.

Role : Design Engineer.

Deliverables for this project are:-

1. Verilog RTL source code

2. Test benches

3. Synthesis and Simulation scripts.

4. Detailed user documentation, including RTL source

code documentation.

JPEG: This project involves complete development of

JPEG on FPGA using verilog. JPEG core contains DCT,

Quantization, RLE and Huffman encoding blocks as sub

modules. All these modules have been developed

individually and integrated to form complete JPEG. My

contribution is in development of DCT, RLE and

Huffman encoding modules.

Client : Achronix.

Duration: 2 months.

Role : Design Engineer.

Matrix Multiplication IP: Matrix multiplication P has

been developed and tested on FPGA using verilog. A

very high performance has been achieved. Mostly

Matrix manipulation IPs finds applications in digital

signal processing applications and communication

systems.

Matrix Transpose: Matrix Transpose IP has been

developed and tested on FPGA. A reasonably high

performance at lower area has been achieved. This IP

finds applications in image compression systems.

DVB-s2 project: This project involves complete

design of DVB -s2 standard on FPGA using verilog.

This DVB-s2 standard consists demodulator and Forward

Error Correction Block (FEC). FEC itself contains BCH

decoder and LDPC decoder. BCH decoder is most widely

used error correction code. Out of 100% codes, BCH

codes occupy 80% area. My part of this is development

of BCH decoder. BCH decoder itself contains sub

modules like syndrome Calculation, Berlekamp

algorithm, chien's search, Forney algorithm etc. All

these modules have been developed individually and

Integrated to form complete BCH decoder. This design

is giving best performance with lower area

requirement.

Project details: 1. Role: Design Engineer.

2. Team size 2.

3. Client: Richsilicon, MIT Labs.

Deliverables for this project are:-

1. Verilog RTL source code

2. Test benches

3. Synthesis and Simulation scripts.

4. Detailed user documentation, including RTL source

code documentation.

BCH Encoder: This project involves complete

development of BCH encoder on FPGA using verilog.

Client : Achronix.

Duration: 2 months.

Role : Design Engineer

Pico-Express Tool IP design and evaluation:

Developing test cases like FFT, DCT and quantization

etc in C and running through the Pico-Express tool

and analysing the performance by including different

pragma's. Reporting tool crashes and bugs like not

achieving required performance with corresponding

pragmas.

Client : Synfora, India.

Duration: 3 months.

Role : Design Engineer.

Fixed point IP design for Pico-Express tool:

Designing fixed point IP's like Fixed point

multiplication, division, shift left and right, and,

or and xnor etc using C. These IP's will be used as

library IP's for Pico-Express tool for fixed point

math.

Client : Synfora, India.

Duration: 3 months.

Role : Design Engineer.

Image processing IP design: All Image processing

algorithms relevant to road traffic analysis are

studied properly. Since edge detection is the basic

IP block of all image processing scenarios, we

started developing SOBEL edge detection algorithm on

FPGA. This includes architecture definition to RTL

development and documentation. This IP design is

completed and it is proved that this is much faster

in speed as compared to software algorithm for edge

detection.

Client Trafficon

Duration : 3 months.

Role : Sr. Design Engineer.

Matrix convolution: Since matrix convolution is basic

building block of all image processing algorithms, we

have developed matrix convolution IP. This includes

final architecture definition, RTL development and

documentation. This is successfully completed.

Client : Trafficon

Duration: 15 days

Role : Sr. Design Engineer.

Sobel Edge detection : Edge detection verilog IP is

implemented on Xilinx FPGA.

Median Filter: Median filter verilog IP is designed

and implemented on FPGA.

Harris Corner Detection: Harris Corner detection IP

is developed using verilog and VHDL and got tested.

Client : Trafficon

Duration: 6 months

Role : Sr. Design Engineer.

SECAM Encoder: SECAM video encoder standard has been

developed on FPGA. This IP is having high quality,

performance and low area.

Client : HDI China.

Duration : 4 months.

GLS (Gate level Simulation): Took ownership for

complete Gate level simulation and it's debugging in

Qualcomm Technologies. And worked with SDF

environment.

Client: Qualcomm Technologies.

Duration: 3 months.

Role : Senior Design Engineer.

Projects done in KLA-Tencor company:

Project Done 1. MMED Board redesign: This project deals with

re designing the existing board. The existing

design is obsolete, and component procurement is

difficult. The goal of this project is to

develop a new MMED, which carries new components

(e.g. FPGAs), eliminates all obsolete

components, all socketed components, all PAL's,

and operates correctly with the existing system

and same functionality. In this the existing

eight (8) each Xilinx XC3130A devices into one

or two new FPGA's. This board contains nearly 68

PAL's and all are coded in ABEL language. All

these PAL's have been decoded into VHDL code

and are incorporated into the FPGA.

2. SRAM failure analysis: This project deals

with determination whether slowing the access

time of SRAM on a board causing them to fail.

Originally the access time of SRAM is 15 ns.

Later it has been changed means the SRAM is

replaced with 35 ns access time. Because of this

70 board failures per year occurred. The logic

of the whole system is understood and then the

block diagram representation of the system has

drawn. Then signal tracing and timing analysis

of the system includes SRAM and all other

components are done.

From the timing analysis it has been concluded

that because of high access time of the memory

chip (35 ns), with in this time two write-write

cycles are coming. Due to it data which is

already written in the memory chip is again

subjected to write statement in the same memory

location. Because of it during that time drive

currents that are fed to the SRAM chip are

violating its drive current limits. The

conclusions of this project are to change the

original SRAM to 15 ns access time.

3. QSB project: This is Quick swap Buffer

project. This aims to increase the throughput

of the double load port handler by using QSB

system instead of using triple handler which

costs high. This system contains foup presence,

placement and pneumatic cylinder sensors.

Depending upon these sensors outputs the

cylinders have to be driven. RS-232

communication is implemented for the data

acquisition digital IO cards (ADAM blocks) which

collects the sensor outputs and then according

to that activates the out put solenoids which

results in the required movement of the load

port and QSB system is achieved.

4. ECWA-VPA project: This projects aims to

incorporate ECWA (Edge contact wafer aligner)

system into Vision pre aligner system.

Client KLA-Tencor Corp. US.

Organization KLA-Tencor Corp. India Private Ltd, Chennai.

Role Electronic System Designer

Duration 10 months

Environment Digital design, Memories, FPGA, PAL.

Roles & Responsibilities:

. Providing equipment to enhance the yield of a semiconductor industry

and hence productivity.

. Defect detection in silicon wafers.

. Innovation in semiconductor industry.

Customer (ex. Intel, TI, IBM etc) satisfaction.

Competency Areas:

Digital Logic Design.

VLSI/FPGA Design

RTL and Verilog.

Digital signal processing applications.

Communication, Error correction codes (RS, BCH etc)

Image compression standard JPEG etc.

VHDL designs.

EDA Tools

Simulation and Synthesis tools

REFERENCES

Prof. Vivek Agarwal, Prof. S. A. Soman,

Dept. of Electrical Engineering, Dept. of Electrical Engineering,

IIT Bombay, IIT Bombay,

Powai, Maharashtra, Powai, Maharashtra,

400076. 400076.

+91-22-257*-**** 022- 25764445

Career Interests

Hardware design ASIC design, RTL & verilog, VHDL, Digital

and Analog design, FPGA Design, CMOS,

Programming Languages VLSI area.

C, C++.

Yours sincerely,

Raghavendra Rao Thota

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