Manager Project

Paul Stiling

Naperville, IL 630-***-****

*********@*****.***

SUMMARY

An experienced engineering professional with management, project

management, and design, verification, and implementation experience in the

development of ASICs, FPGAs, and telecommunications and data communications

products. Experienced working with a worldwide team. Effective at leading

teams and project management to ensure projects are high quality, completed

on time completion and within budget.

PROFESSIONAL EXPERIENCE

TELLABS, Naperville, IL 1997 - 2011

Senior Engineering Manager (2000 - 2011)

Hardware engineering: module level, FPGA, and ASIC development for optical

transport system. Project teams successfully developed new products,

managed prototype fabrication and testing, transitioned to manufacturing,

and released for general availability.

. Designed a > 1 Tb/s distributed switch for an optical transport system

supporting Optical Transport Network (OTN) interfaces. Project

included data interfaces > 1 Gb/s

. Developed 5 custom ASIC and FPGA devices that supported SONET, SDH,

DS3 / T1, Ethernet, and Fibre Channel interfaces and Digital Signal

Processing for Echo cancellation

. Performed chip level simulation for 3 devices using procedure based

self checking test benches (C++, VHDL, and Verilog) and assertions and

constrained random inputs (System Verilog)

. Performed synthesis, timing analysis, formal verification, and test

logic insertion for 3 ASICs

. Created manufacturing test vector generation: boundary scan, RAM BIST

(including handling RAMs with redundant memory cells), random logic,

IDDQ, and delay for 2 ASICs

. Created 3 ASIC product proposals resulting in cost reductions for

existing products

. Selected ASIC device library and tool vendors, documented new

development processes allowing internal ASIC development at smaller

geometries with 50% reduction in development costs

. Negotiated statements of work (SOW) with design services firm and

managed their project work

Development Manager (1999 - 2000)

. Selected tool vendors and created on-line process documentation

. Managed tool vendor relationships, negotiated license agreements and

pricing

. Led development of one ASIC project.

. Created scripted design flow; trained and mentored department members.

Lead Engineer (1997 - 1999)

. Designed and verified 2 ASIC devices implementing SONET, SDH, and

DS3/T1interfaces.

. Performed synthesis, timing analysis. test logic insertion (DFT), and

test vector generation

US ROBOTICS / 3COM, Mt Prospect, IL

1996 - 1997

Section Manager

Led the development of new rack mounted data communication product with

Ethernet over SONET mapping.

AT&T BELL LABORATORIES, Naperville, IL 1981 - 1995

Member of Technical Staff

Developed telecommunications hardware, firmware, and DSP software.

Developed ASICs for broadband digital cross connect product.

EDUCATION

Master of Science Electrical Engineering Purdue University

West Lafayette, IN

Bachelor of Science Electrical Engineering Purdue University

West Lafayette, IN

AWARDS AND PUBLICATIONS

. "VLSI Design Process", Session Award Winner, Tellabs Current Practices

Seminar, June 2001

. US Patent 5,444,716 - Boundary-scan-based system and method for test

and diagnosis, August 22, 1995

. "5ESS-SM2000 Switch: The Next Generation Switching System", AT&T

Technical Journal, Sept. 1993

. "A Framework for Boundary-Scan Based System Test and Diagnostics",

IEEE Workshop on Design for Testability, April 1992

. "A System Design For Real Time Signal Processing", IEEE Conference on

Acoustic, Speech, and Signal Processing, April 1986

TECHNICAL SKILLS

. Expert in the following ASIC / FGPA software tools:

o Mentor Graphics

. HDL Designer - design capture

. Modelsim - device simulation

o Synopsys

. Leda - HDL source code lint tool

. vcs - simulation

. DesignCompiler - synthesis

. DFT Compiler - test logic insertion

. PrimeTime & PrimeTime SI - timing analysis & signal integrity

. Formality - formal verification

. Star-RC-XT - parasitic extraction

. Tetramax - test vector generation

. BSDL Compiler - boundary scan test

o Cadence

. Celtic - signal integrity and incremental timing analysis

o IBM Rational

. ClearCase - source control

. ClearQuest - issue tracking

. Expertise in VHDL, Verilog, SystemVerilog, C, C++, perl, awk, set,

tcl, sdc, makefiles, LINUX

. Experienced creating verification environments with high level drivers

and monitors (C and creating tests using assertions and

constrained random inputs (VMM / OVM)

. Expert User of the following software tools:

o Microsoft Office products: Outlook, Word, Excel, PowerPoint, Visio

o Microsoft Project and Project Server

o Microsoft SharePoint

o Adobe FrameMaker

. Trained in program management (PMP / PMI)

. Internal auditor for conformance to TL9000 / ISO9001 requirements

Contact this candidate