Engineer Design

Jessica Chin

Tel: 408-***-****

E-mail:***********@*********.***

SUMMARY:

Over 10+ years of experience in ASIC Design Engineering, working in a

fast-paced schedule

environment to bring up working silicon for company next

generation main-line products.

Well versed in ASIC design flow including design architecture, RTL

code implementation,

synthesis, DFT insertion, ATPG, static timing analysis, function

verification, timing closure,

prototype chip bring up, silicon validation, and test coverage for

manufacture.

Plus years of experienced in FPGA, and Firmware design engineering.

A dedicate, deliberate, proactive worker; quick-learner; a teamwork

player, goal-driven engineer.

TECHNICAL SKILLS:

Operating System: Sun Solaris, Unix/Linux, Microsoft Windows, MS-

DOS.

CAD/Lab tools: Synopsys DC/DV, PT, VCS, NCSIM, Verilint, Verplex,

Verdi/Debussy,

Mentor Graphics schematic capture design tools, Xilinx ISE;

Logic Analyzer, Oscilloscope.

Knowledge: PCI-Express, PCI-X, PCI, SAS, SATA, SCSI, AHB/APB, EISA,

ISA, SMB, I2C,

ARM, SDR/DDR, SVA, OVA, OVM/VMM, STA, DFT, MBIST, BSD, JTAG.

Languages: Verilog-XL, VERA, SystemVerilog, Specman e, C/C++, Shell

Scripts, Perl, TCL, Assembly, HTML, PHP.

EXPERIENCE:

Sr. Staff Engineer (01/08 - 06/10)

SanDisk Corporation

[Web page: http://www.sandisk.com/]

. Designed and verified a high speed host interface model with

SystemVerilog for memory controller design updated feature.

Automation scripting effort included.

. Architectured and implemented a test bench with SystemVerilog to

enhance controllability, test coverage, reusability and

flexibility.

. Team worked on assertion checking to complete memory design timing

verification.

Sr. Staff Design Engineer (09/06 - 10/07)

ALinks Communications, Inc., 530 Lakeside Drive, CA 94086

[Web page: http://www.issc.com.tw/]

. Completed on Wireless application SOC design integration with brand

named 32-bit CPU core IP and AMBA 2.0 AHB/APB compliant devices IP.

. Experienced on working design verification with a Verilog,

SystemVerilog and C mixed test bench with reuse methodology/class

library such as OVM/VMM.

. Enhanced design with PCI-E interface, debugged and verified design.

Sr. ASIC Design Engineer (03/05 - 08/06)

Promise Technology, Inc., 580 Cottonwood Drive, CA 95035

[Web page: http://www.promise.com/]

. Completed SAS/SATA PHY core Physical Coding Sublayer PHY OOB engine

design specification, Verilog code implementation, integration,

functional verification, synthesis, and STA timing closure to

achieve design validation with internal 300Mhz clock rate for a

four-channel 3G SAS/SATA PHY Mixed Signal Design.

. Completed PCS block synthesis, STA, DFT flow and removed test

errors, ATPG, for test coverage.

. Built block sim. and test automation. Labored with team to bring up

the prototype chip.

Sr. ASIC Design Engineer (11/95 - 09/04)

Adaptec Inc., 691 South Milpitas Blvd., Milpitas, CA 95035

[Web page: http://www.adaptec.com/]

. Designed a test program to verify the functionality of a 3G

SAS/SATA PHY Mixed Signal Design with Xilinx Virtex-II FPGA device

implementation, and responsible for signal integrity measurement

with BERT analyzer. Another test program defined and developed with

FPGA implementation for a chip in 2.5G PCI-Express application is

as well.

. Developed manufacture test vectors generation with VERA programming

and test bench environment to complete an eight-channel 3G SAS/SATA

prototype chip silicon verification and validation.

. Completed DMA portion of SCSI core design for SPI-4 320Mhz

Packetized PCI-X/SCSI Host Adaptor; finished full product

development process including micro-architecture

of the design, design specification, logic implementation with

Verilog, formal verification with Verplex, synthesis, post-layout

timing closure with Synopsys tools; responsible for block-level

test planning, functional/timing verification, prototype chip on

board debugging, intensively compatible testing, and manufacture

test vector coverage.

. Completed a Serial EEPROM control interface design and function

verification with

HDL Verilog for an SPI-3 Host Adaptor controller chip applied on

PCI-X mother board.

. Completed the logic design modification and verification with

schematic capture for PCI power management interface on PCI to SPI-

2 SCSI Host Adaptor chip.

. Completed design modification, and verification with VHDL and HDL

Verilog for SCSI CD-ROM controller chip. Conducted whole chip

synthesis and Static Timing Analysis with Synopsys Design Compiler

for timing closure to tape out chip.

. Improved block-level test coverage to 97% with ATPG test pattern

and at speed test pattern in half-scan design.

. Verified prototype chip with lab testing, debugging and generated

manufacture test vector for test coverage improvement. Finished AC

timing measurement for timing specification.

ASIC Design Engineer (6/93 - 11/95)

BusLogic Co., 2366 Mission Blvd., Santa Clara, CA 95134-2037

. Completed design specification and code implementation with Verilog

for a hard disk controller chip applied on PCI/SCSI Host Adaptor

. Completed design and modification with Mentor Graphics schematic

capture data base of

The in-house hard disk controller chip applied on SCSI Host Adaptor

Board.

. Conducted chip integration, test vector generation and function

verification with Verilog simulation, and finished prototype chip

verification on test bench.

Firmware Engineer, ASIC Verification Engineer (12/90 - 6/93)

UltraStor, Co., 3561 Warm Springs Blvd. Fremont, CA 94538

. Responsible for function verification of in-house chip design with

Verilog and simulation.

. Technical support for company products with co-workers, and

prepare product spec.

EDUCATION:

Digital Signal Processing, Fundamentals UCSC Extension, Santa

Clara, CA U.S.

Mixed-Signal IC Design, PLL and Clock/Data Recovery Circuits

Wright State University, M.S. in Electrical Engineering, Ohio, U.S

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