mtech with 1.8years exp in analog layout design
Resume:
CURRICULUM VITAE
CHAKRAPANI S
ADDRESS: S/O VENKATESH S, E-mail: ************@*****.***
#***, **** *****, **** ***** ring road, Alternate ID: *******@*****.***
Domlur Layout, Contact : 903-***-****
BANGALORE – 560071 : 080-********
CAREER OBJECTIVE:
To apply and expand my engineering skills in the field of VLSI design, with the opportunity to work on projects from conception to completion.
EDUCATION:
EXAMINATION INSTITUTION YEAR OF COMPLETION PERCENTAGE
M.Tech(VLSI Design) East Point College of Engineering & Technology,B’lore 2012 70.91
B.E (Electronics & Communication) BTL Institute of Technology, Bangalore
2008
65
EXPERIENCE:
Company : Bharat Electronics Limited (BEL), Bangalore
Department/Division : IC Design Centre
Area of work : Analog circuit & layout design
Period : 1.8years
PROJECTS undertaken at BEL:
Project I:
Title: CMOS Circuit Design, Simulation and Physical Design of a Two Channel Demodulator ASIC
Description: Two-channel demodulator consists of four inputs which are analog & two outputs of dc signals. Based on analog multiplexer select pin any one channel is selected out of two channels for processing, each channel consists of two inputs. Demodulator section consists of precision full wave rectifier, 2nd order Butterworth low pass filter, summing & difference amplifiers. The input differential analog signals are rectified & filtered independently to get v1& v2.Filtered outputs are added, subtracted & amplified to get -(v1+v2) & (v2-v1) respectively which are of bipolarities.
Contribution: Circuit & Layout design of OPAMP, Analog Multiplexer(Inverter,buffer,AND,Decoder,TG), Precision Full wave Rectifier, 2nd order Low pass Butterworth Filter, Summing Amplifier, Difference Amplifier, integration of all the blocks(Full block).
CAD Tools used:
• Circuit design : cadence VIRTUOSO schematic editor
• Circuit Simulation : cadence SPECTRE
• Layout design : cadence VIRTUOSO layout editor
• Layout Verification(DRC & LVS) : Mentor Graphics CALIBRE
Presented paper for National conference on Communication and Soft Computing (NCCSC-2012) at K S Institute of Technology, Bangalore.
Project II:
Title: Design of power supply ASIC for night vision devices.
Description: This power supply is used for image intensified tubes in night vision device. The ASIC Controls the anode, cathode & Micro Channel Plate (MCP) supply voltages of the image intensified tube through two regulator circuit’s .It incorporates external gain control & automatic brightness control.
Contribution: 1. Layout (Design & Verification) of BANDGAP REFERENCE.
2. Layout (Design & Verification) of OPAMP.
3. Transistors Matching, Electro migration & other layout concepts
have been implemented in the layouts.
4. Basic practical knowledge of Bond padding, Floor planning, GDSII conversion etc
CAD Tools used:
• Layout Design : Cadence VIRTUOSO Layout Editor
• Layout Verification(DRC & LVS) : cadence DIVA & Mentor Graphics CALIBRE
Project III:
Title: Driver for High Drive LED-ASIC.
Description: Driver for high drive LED is an Application Specific Integrated Circuit for battery operated white LED to be use in portable devices. It has to drive 650ma constant current to the LED. It has to start working at 1v startup voltage from battery & has to deliver this current even when the battery discharges from its steady 3.3v down to 0.4v.Hence it uses the boost converter DC to DC converter since it provides a constant load current.
Contribution: 1. Layout (Design & Verification) of COMPARATOR.
2. Layout (Design & Verification) of BANDGAP REFERENCE.
3. Transistors Matching, Electro migration & other layout concepts
have been implemented in the layouts.
4.Basic practical knowledge of Bond padding, Floor planning, GDSII conversion etc
CAD Tools used:
• Layout Design : Cadence VIRTUOSO Layout Editor
• DRC, ERC, and LVS : Cadence DIVA
Project IV:
Title: Micro Sun Sensor (MSS).
Description: An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micro machined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photo detectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS.
Contribution: 1. MASK Layout Design of Micro sun sensor.
2. Individual cell masks of Micro sun sensor (N++ diffusion mask, P++ diffusion
mask, Metallization mask,Anti reflection coating mask, Slit pattern mask, mask for Cavity etching on Pyrex).
CAD Tool used:
• Layout Design : Cadence VIRTUOSO Layout Editor
TECHNICAL EXPOSURE:
Full Custom Layout design (CMOS), Bipolar & CMOS circuit design and simulation, Standard Cell design (CMOS), Layout Verification (DRC, LVS).
EDA TOOLS SKILLS:
CADENCE tools suite:
Circuit Simulation : SPECTRE
Layout Design : VIRTUOSO Layout Editor
DRC, LVS : DIVA.
Mentor Graphics:
DRC, LVS : CALIBRE
TANNER:
Schematic : S-Edit
Layout : L-Edit
Silvaco:
Schematic Editor : Gateway
Layout Editor : Expert
SKILL SET:
Assembly languages : µp 8085, 8086 & µc 8051.
Platforms : Windows XP, UNIX.
Scripting Languages : PERL
Programming Languages : C, C++.
Hardware Languages : VHDL.
PERSONAL DETAILS:
Date of Birth : 13th February 1986
Father’s Name : Venkatesh S
Languages Known : English, Kannada, Telugu and Tamil.
EXTRACURRICULAR ACTIVITIES AND INTERESTS:
• Presented paper for National conference on Communication and Soft Computing (NCCSC-2012) on 9th August 2012 at K S Institute of Technology, Bangalore.
• Dance, Cricket, Carrom, Chess & Football.
REFERENCE:
1. Karthik 2. Kiran
Deputy Manager, IC Design Centre, Senior Engineer, IC Design Centre,
Bharat Electronics Limited (BEL) Bharat Electronics Limited (BEL)
Bangalore-560013. Bangalore-560013.
Ph: 990******* Ph: 998-***-****
Email: ********@***.**.** Email: *********@*****.**.**
DECLARATION:
I hereby declare that all the details furnished above are true to the best of my knowledge.
Place: Bangalore _________________
Date: (Chakrapani S)
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