Design Power

HAIQING NAN

Address: **** *. ********* ******,

Email: ************@*****.***

Chicago, IL, 60616, USA

Phone: +1-312-***-****

Objective & Research Experience:

To obtain a full-time position utilizing my research skills (listed as

follows) on VLSI Design

1. Design for Power (DFP): ultra-low-power techniques from system

level to circuit level

2. Design for Manufacturing (DFM): process variation compensation and

yield optimization

3. Digital integrated circuit design

4. Highly reliable digital circuit design considering soft error and

aging effects (HCI, NBTI, TDDB).

5. Circuit design for new materials (carbon nanotube FET)

Education:

Illinois Institute of Technology, Chicago, IL, Ph.D. Electrical

Engineering: GPA:3.6/4.0: expected December 2011

Academic Project:

< UHF RFID System Design and Implementation for EPC C1G2 spec, Jan 2010-Jan

2011 Sponsored by LG, Korea.

< Matlab Simulink Modeling and Simulation

< Verilog Implementation for RFID System According Class-1 Gen-2 Spec.

< FPGA Board Verification and Demonstration

Illinois Institute of Technology, Chicago, IL, M.S. Electrical Engineering:

GPA:3.88/4.0: May 2008

He Bei University of Technology, Tianjin, China, BMEE Electrical

Engineering: GPA:3.5/4.0: July 2006

Experience:

DA-LAB Illinois Institute of Technology, Chicago, IL. Research

Assistant Sept. 2008-Present

( Ultralow Voltage Power Gating Using Low Threshold Voltage in 45nm

Technology

< Power Gating Footer Design Using Low Threshold Voltage Device

< Sub-threshold Leakage and Gate Leakage Reduction Scheme Design Using

Power Gating

< Step Wise Wakeup Mechanism Design for Power Gating Cell Using HSPICE

( Dynamic Voltage and Frequency Scaling for PVT Variations in 45nm

Technology

< PVT Variation Analysis on Digital Circuits

< A/D Converter, Look-up Table with Voltage Regulator Implementation

Using HSPICE

< PVT Variation Compensation Design Using Dynamic Supply Voltage

Scaling

( Adaptive HCI-Aware Power Gating Structure in 45nm Technology

< HCI Effect Analysis on Digital Circuit Using MATLAB

< HCI Monitoring Circuit, Look-up Table and A/D Converter Design Using

HSPICE

< Power Gating Cell with Tunable Footer Size Design to Tolerate HCI

( Soft Error Hardening Design of Nanoscale CMOS Latch in 32nm/45nm

Technology

< Soft Error Analysis and Modeling for Deeply Scaled Technology

< Hardened Latch Circuit Design to Tolerate Soft Error on Digital

Circuits

< Layout and Verification Using HSPICE

( Hybrid Power Gating with Ultralow Voltage in 32nm Technology

< Power Gating Cell Design Using CMOS and CNFET

< Step Wise Wakeup Mechanism Design for Hybrid Power

Gating Using HSPICE

( Ternary Logic Family Design Using CNFET

< Analysis of CNFET Back Biasing Effect

< CNFET Based Ternary Logic Family and Arithmetic Circuit

Design Using HSPICE

< Mis-aligned and Mis-positioned CNTs Immune Layout

Method for CNFET Circuit

( CNFET SRAM Design Using Optimum Back Biasing Voltages

< Back Biasing Voltages Optimization for CNFET Based SRAM

( TDDB Monitoring Circuit and Compensation Method for Nanoscale CMOS

Circuits

< TDDB Sensor Circuit Design in 32nm Technology

< A/D Converter, Look-up Table Design Using HSPICE

Motorola Co., LTD. System Testing Engineer

June 2007-June 2008

( Hardware and Software Testing for Mobile Handsets

( Cellular Phone Performance Analysis and Improvement

Skills:

( Language: C, perl, VHDL, Verilog.

( CAD Tools: Hspice, Design Compiler, IC Compiler, PrimeTime,

Formality, Virtuoso, Modelsim, Matlab

Awards:

( Best Paper Award for ISOCC 2010 Conference

( Best Paper Award for ISOCC 2009 Conference

( Best Research Poster Award for Poster Competition in Illinois

Institute of Technology, 2009

Selected Publications:

1] Haiqing Nan, and K-w Choi, "Inter-hierarchical power analysis

methodology to reduce multiple orders of magnitude run-time without

compromising accuracy, " IEEE International SoC Design Conference

(ISOCC), 2009, pp. 556-559. (Best Paper Award)

2] Kyung Ki Kim, Haiqing Nan, and K-w Choi, "Adaptive HCI-aware power

gating structure, " IEEE International Symposium on Quality Electronic

Design (ISQED), 2010, pp. 219-224.

3] Kyung Ki Kim, Haiqing Nan, and K-w Choi, "Ultralow-Voltage Power Gating

Structure Using Low Threshold Voltage, " IEEE Trans. Circuits and

Systems II, vol. 56, no. 12, pp. 926-930, 2009

4] Kyung Ki Kim, Haiqing Nan, and K-w Choi, "Power Gating for Ultra-Low

Voltage Nanometer ICs", IEEE ISCAS, pp. 1472-1475, 2010.

5] Haiqing Nan, Kyung-ki Kim, Wei Wang and Ken Choi, "Dynamic Voltage and

Frequency Scaling for Power-Constrained Design using Process Voltage and

Temperature Sensor Circuits", Journal of Information Processing System,

2011

6] Haiqing Nan and Ken Choi, "Novel Radiation Hardened Latch Design

Considering Process, Voltage and Temperature Variations for Nanoscale

CMOS Technology", Elsevier Microelectronics Reliability, 2011

7] Haiqing Nan and Ken Choi, "Novel Ternary Logic Design Based on CNFET",

IEEE International SoC Design Conference (ISOCC), 2010

8] Haiqing Nan and Ken Choi, "Novel Soft Error Hardening Design of

Nanoscale CMOS Latch", IEEE International SoC Design Conference (ISOCC),

2010 (Best Paper Award)

9] Sandeep Suhas, Haiqing Nan and Ken Choi, "Low Power Latch Design in Near

Sub-threshold Region to Improve Reliability for Soft Error", IEEE

International Symposium on Quality Electronic Design (ISQED), 2011

10] Lili, Haiqing Nan and Ken Choi, "Effective Algorithm for Integrating

Clock Gating and Power Gating to Reduce Dynamic and Active Leakage Power

Simultaneously", IEEE International Symposium on Quality Electronic

Design (ISQED), 2011

Contact this candidate