Engineer

JAYASHREE.P

*/**,*** ******,******** nagar,

Chinmaya nagar(EXTN), E-mail:***************@*****.***

Virugmbakkam, Chennai-600 092 Mobile: 956-***-****

OBJECTIVE

To become a contributing Professional in an organization for its success, by applying the

best business practices, through innovative solutions and constantly updating my skills. I would

like to be in a team, where there is emphasis towards continuous learning and individual

contributions are also given duty recognition.

EDUCATIONAL QUALIFICATION

YEAR QUALIFICATION INSTITUTION UNIVERSIY/ PERCENTAGE/

BOARD CGPA

2009- B.E [ECE] S.B.C. ENGG COLLEGE, ANNA 7.98

2013 THIRUVANNAMALAI. UNIVERSITY

CHENNAI

2009 HSC S.R.K.M.SARADA STATE 76%

VIDHAYALAYA GOVT BOARD

GIRLS HR.SEC

SCHOOL,CHENNAI

2007 SSLC JAIGOPAL GARODIA STATE 83%

GOVT GIRLA HR.SEC BOARD

SCHOOL,CHENNAI

AREA OF INTEREST

VLSI, Digital Electronics.

Windows 2000,XP,Windows 7.

Networking.

ACADAMIC

SOFTWARE

COURSES

OPERATING SYSTEM

COMPUTER MS OFFICE

KNOWLEDGE

LANGUAGES HDL,Verilog HDL,C,C++.

TOOLS Xilinx,Modelsim,MATLAB.

PROFESSIONAL ACTIVITIES

In Plan Training:

Under gone In Plan Training in Bharat Sanchar Nigam Limited(BSNL)

at T.V. Malai(Dt).

PRESENTATION:

Presented Paper named ALTERNATIVE FUELS FOR KEROGEN held in

S.K.P.Engineering College, T.V.Malai.

Presented Paper named VLSI IMPLEMENTATION OF EVOLUABLE PID

CONTROLLER held in Tamilnadu College Of Engineering, Coimbatore.

Presented Paper named WIRELESS COMMUNICATION held in Sri Nandhanam

College Of Engineering & Technology,Tirupattur.

CONFERENCE:

Presented Paper named EMBEDDED SYSTEM held in VEL TECH, Chennai

WORKSHOP:

Participated in ROBOTICS workshop held in SBC ENGINEERING COLLEGE at Arni

through IIT BOMBAY.

Participated in NATIONAL LEVEL workshop on VLSI DESIGN held in SBC

ENGINEERING COLLEGE at Arni through VIT University.

OTHER ACTIVITIES

Assist.Coordinator for our Department workshop on VLSI DESIGN.

Treasurer for our Department Symposium.

ACADEMIC PROJECT

TITLE: DESIGN OF AES BASED ON FPGA IMPLEMENTATION.

DESCRIPTION:

The Main theme of our Project is FPGA implementation of an AES

encryptor/decryptor using an iterative looping approach with block and keysize of 128

bits. This method may gives very low complexity architecture and is easily operated to

achieve low latency as well as high throughput.

ALGORITHM: AES,DES.

LANGUAGE: Verlog HDL.

TOOLS: XILINX, Model Sim

PERSONAL INFORMATION

Date of Birth : 22/05/1992

Gender : Female

Father name : S. Padma sekar

Mother tongue : Tamil

Nationality : Indian

Marital Status : Single

Languages : Tamil, English.

DECLARATION

I do herby declare that the particulars of information and facts stated herein above are true,

correct and complete to the best of my knowledge and belief.

Yours truly,

PLACE: CHENNAI (P.JAYASHREE)

DATE :

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