Project Engineering

Resume

Email: *********@*****.***,

Ameer Basha Shaik

Flat no: 204,

AnjanaTowers,

Mallapur,

Hyderabad-500076

Career Objective:

To contribute to the overall growth of the organization where I can

effectively contribute my skills as Hardware and Software Professional.

Posses competent Technical Skills. Have a result oriented approach. And

want to achieve excellence in the job assigned to me, while continuously

gaining knowledge and learning new things.

Educational Qualification:

M.Tech. (VLSI System Design) CVR College of Engineering, Hyd, 2011-2013, 77

%

(Till 3rd semester)

B.Tech (Electronics & Communication) Shadan college of engineering and

technology, Hyd, 2006-2010, 66.97%

H.S.C. (12th std.) Sujatha Junior College, Ponnur (Board of Intermediate

Education-Andhra Pradesh) 2004-2006, 88.2 %

I.C.S.E(10th std) St.Ann's School, Ponnur 2003-2004,55%

Projects Undertaken in M.Tech:

Thesis Project:

1. Project Title: Design and Implementation of a High Speed and Low Power 8-

bit Folding and Interpolating ADC using 0.18um CMOS process.

Organization: CVR College of Engineering, Hyderabad.

Duration: 12 Months.

Hardware / Tools: Cadence virtuoso Schematic and Layout Editor, RF spectre

simulator, HSPICE and MATLAB r2009 simulink simulator.

Platform: UNIX, Windows XP.

Project Guide: G.Shilpa Kesav, Assistant Professor. CVR College of

Engineering, Hyd.

Description: This project is about designing and implementing a high speed

and low power 8-bit ADC used in the front end part of the receivers in RF

communication circuits and in HD Televisions. The design of the ADC is

implemented in 0.18um CMOS process using Cadence Virtuoso Schematic Editor

and the simulation is carried out using RF spectre simulator, the layout is

drawn using Cadence Virtuoso Layout Editor and the static and dynamic

characteristics of the ADC are obtained by using the MATLAB simulink

simulator.

2. Project Title: Full Custom Design of Single Ended Two Stage Operational

Amplifier.

Organization: CVR College of Engineering, Hyderabad.

Duration: 2 Months

Hardware / Tools: Cadence virtuoso Schematic and Layout Editor, RF spectre

simulator.

Platform: UNIX.

Project Guide: R.Ganesh, Sr. Assistant Professor, ECE, CVR College of

Engineering, Hyd.

Description: The full design starting with the basic equation without

compensation, Again redesigned the circuit with compensation, Schematic

Entry, The extensive Simulation for all design parameters has been done,

like process corner, transistor size and temperature, Then Layout with rule

checks, Verification with schematic,

parasitic estimation and Post Layout simulation has been done.

Project Undertaken in B.Tech:

3. Project Title: Implementation of a call concierge using FPGA

Organization: TELEPARADIGM INSTITUTE, Hyd.

Duration: 4 Months

Hardware / Tools: OPEN AT & M2M Studio.

Description:

The prime objective of this project is mainly developed to convert the

voice calls into AMR format and mail to the user's email id, and keep track

records of all the received calls, messages and the voice mails without any

consumption of charge. This project is implemented in embedded c

programming language and simulated on M2M Studio simulator and is

downloaded onto a module FASTRACK SUPREME-10, made by TEXAS INSTRUMENTS on

the OPEN AT environment.

Skill Set

. Languages: C, Embedded C and Assembly Language.

. Tools: Xilinx ISE 12.2, Cadence virtuoso Schematic Editor, Cadence

virtuoso Layout

Editor MATLAB r2009

. Hardware: Xilinx Virtex-5 FPGA, Xilinx Spartan-3E FPGA.

. Simulation Packages: MATLAB, HSPICE and Spectre.

. HDLs: Verilog, VHDL, and C.

. Operating System: UNIX, Windows XP, Windows7.

Co Curricular and Extra-Curricular Activities

. Volunteered in NATIONAL Workshop For VLSI Design using Standard cells

using

Cadence Tools at CVR College of Engineering, Hyderabad

. Attended the NATIONAL Workshop for PHYSICAL DESIGN OF ASIC using

Cadence First Encounter Tools at CVR College of Engineering, Hyd.

. Presented a paper on "Design of a Low Power and high speed 8-bit Folding

and

Interpolating ADC" at CIENCIA, 2013, a National level Technical Fest

held at CVR

College of Engineering & Technology

. Presented a paper on "Free Space Optics" at TECHNO SPIRIT-2, 2010, a

National level Technical Fest held at Shadan College of Engineering &

Technology.

. Active participant in college in social and cultural activities

Personal Details

Date of Birth : 16th January, 1988

Father's name : Mr.Mahaboob Subhani

Nationality : Indian

Languages Known : English, Hindi

Hobbies / Interests : Playing Cricket, Chess and Travelling

Declaration:

I hereby solemnly affirm that all the details furnished

above are true to the best of my knowledge.

Place: HYDERABAD

Date: 07-09-2013

AMEER BASHA.SHAIK

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