| Resume alert | Resumes 1 - 10 of 202 |
First Class Front End
Hyderabad, Telangana, India
... RTL Design using VHDL/Verilog. Synthesis and Simulation using Xilinx ISE, Vivado & Modelsim. RTL development, resolving system level challenges, architecting, implementing, and documenting using Verilog/VHDL concepts. The programming of FPGAs ... - 2023 Sep 19
... RTL Design using VHDL/Verilog. Synthesis and Simulation using Xilinx ISE, Vivado & Modelsim. RTL development, resolving system level challenges, architecting, implementing, and documenting using Verilog/VHDL concepts. The programming of FPGAs ... - 2023 Sep 19
Manual Testing Life Cycle
Hyderabad, Telangana, India
... VLSI : VHDL, MATLAB Title : Design RF Ring oscillator using current mode technology Domain : Image processing. Language : VLSI Objective : The objective of this project is to provide the security and time managing For any co-operation or institute ... - 2023 Aug 31
... VLSI : VHDL, MATLAB Title : Design RF Ring oscillator using current mode technology Domain : Image processing. Language : VLSI Objective : The objective of this project is to provide the security and time managing For any co-operation or institute ... - 2023 Aug 31
Software engineer
Hyderabad, Telangana, India
... As Ex-Data Analyst in Globaledx Technologies from Jul2016-Sept2016 ACADEMIC PROJETCS EVM TRIPLE DATA ENCRYPTION STANDARD USING VERILOG/VHDL SECURITY FROM SINGLE TO MULTI CLOUD USING JAVA Skill set Interpersonal skills and Java PERSONAL ATTRIBUTES ... - 2021 Dec 10
... As Ex-Data Analyst in Globaledx Technologies from Jul2016-Sept2016 ACADEMIC PROJETCS EVM TRIPLE DATA ENCRYPTION STANDARD USING VERILOG/VHDL SECURITY FROM SINGLE TO MULTI CLOUD USING JAVA Skill set Interpersonal skills and Java PERSONAL ATTRIBUTES ... - 2021 Dec 10
Vellore D S
Hyderabad, Telangana, India
... power Digital Electronics Quantum Neural Network CERTIFICATION COURSES Modelling of Digital logic circuits designing using VHDL conducted by TBI Attended Two days Training Programme on “Semi Custom and Full Custom VLSI Design using Cadence EDA Tool” ... - 2021 Sep 27
... power Digital Electronics Quantum Neural Network CERTIFICATION COURSES Modelling of Digital logic circuits designing using VHDL conducted by TBI Attended Two days Training Programme on “Semi Custom and Full Custom VLSI Design using Cadence EDA Tool” ... - 2021 Sep 27
Cgpa Agriculture
Hyderabad, Telangana, India
... 8 CGPA Intermediate(MPC) Sri Chaitanya Junior College,Vijayawada 2016 96% SSC SMKZP high school,movva 2013 9 CGPA • Basics of C • VHDL Coding • Basics of Verilog • MATLAB • FIELD CONTROLLING AND MONITORING: An IOT based application in the field of ... - 2021 Jul 16
... 8 CGPA Intermediate(MPC) Sri Chaitanya Junior College,Vijayawada 2016 96% SSC SMKZP high school,movva 2013 9 CGPA • Basics of C • VHDL Coding • Basics of Verilog • MATLAB • FIELD CONTROLLING AND MONITORING: An IOT based application in the field of ... - 2021 Jul 16
Industrial Training Project
Hyderabad, Telangana, India
... TECHNICAL SKILLS Operating Systems : Windows XP/2000/2003 Languages : Basics of C & Python Scripting languages : VHDL Software : Model SIM, Matlab Packages : MS Office AREA OF INTEREST Embedded Systems PERSONAL SKILLS Having zeal to flourish in the ... - 2021 Jul 15
... TECHNICAL SKILLS Operating Systems : Windows XP/2000/2003 Languages : Basics of C & Python Scripting languages : VHDL Software : Model SIM, Matlab Packages : MS Office AREA OF INTEREST Embedded Systems PERSONAL SKILLS Having zeal to flourish in the ... - 2021 Jul 15
Embedded System Project Development
Hyderabad, Telangana, India
... • Research & Development of the modules in the product Electronic Corporation of India Limited May 2018- July 2018 Project 2: Optimal Design of Reversible Parity Full Adder Sub-tractor Technologies Used: Verilog, VHDL Team Size: 3 Members Role: ... - 2021 Jun 02
... • Research & Development of the modules in the product Electronic Corporation of India Limited May 2018- July 2018 Project 2: Optimal Design of Reversible Parity Full Adder Sub-tractor Technologies Used: Verilog, VHDL Team Size: 3 Members Role: ... - 2021 Jun 02
Colony Irrigation
Hyderabad, Telangana, India
... VHDL programming. WORKSHOPS Participated in ”PCB(PRINTED CIRCUIT BOARD)” design at KHIT organized by APSSDC. Participated in “ENTREPRENEURSHIP” at KITS. ACHIEVEMENTS Participated “smart irrigation” paper presentation in SAMKALP at KHIT. Participated ... - 2021 May 23
... VHDL programming. WORKSHOPS Participated in ”PCB(PRINTED CIRCUIT BOARD)” design at KHIT organized by APSSDC. Participated in “ENTREPRENEURSHIP” at KITS. ACHIEVEMENTS Participated “smart irrigation” paper presentation in SAMKALP at KHIT. Participated ... - 2021 May 23
Embedded/IOT developer
Hyderabad, Telangana, India
... • Attended minor training in VHDL. • One week Faculty and Training Program on Robotics and Embedded System from IIT Roorkee. • Attended workshop on Analog IC DESIGN using Cadence Design Flow . ACHIVEMENT • Qualified GATE Exam in 2017 with 88.65 ... - 2021 Mar 18
... • Attended minor training in VHDL. • One week Faculty and Training Program on Robotics and Embedded System from IIT Roorkee. • Attended workshop on Analog IC DESIGN using Cadence Design Flow . ACHIVEMENT • Qualified GATE Exam in 2017 with 88.65 ... - 2021 Mar 18
Engineering Design
Hyderabad, Telangana, India
... STATE 2012-2014 86 X Class KAKATIYA MODAL HIGH SCHOOL SSC 2011-2012 93 Skills Set: Programming Languages: C, Embedded C, Verilog and VHDL Testing : DFT. Softwares : Keil, Xilinx Ise,Tina Pro, Cisco, Arduino IDE, Matlab, Mentorgraphics. Operating ... - 2021 Mar 11
... STATE 2012-2014 86 X Class KAKATIYA MODAL HIGH SCHOOL SSC 2011-2012 93 Skills Set: Programming Languages: C, Embedded C, Verilog and VHDL Testing : DFT. Softwares : Keil, Xilinx Ise,Tina Pro, Cisco, Arduino IDE, Matlab, Mentorgraphics. Operating ... - 2021 Mar 11