| Resume alert | Resumes 1 - 6 of 6 |
Engineer Assistant
Bhubaneswar, Odisha, India
... 2 81.2 Certification Academics Verilog Language PCB Design Microsoft Office Adobe Creative Suite Hands-on experience with Lab Equipment adh4ni@r.postjobfree.com +91-766******* Achievements Won 2nd prize for Solar tracker Model in Rungta Technical Fest. ... - 2020 Nov 25
... 2 81.2 Certification Academics Verilog Language PCB Design Microsoft Office Adobe Creative Suite Hands-on experience with Lab Equipment adh4ni@r.postjobfree.com +91-766******* Achievements Won 2nd prize for Solar tracker Model in Rungta Technical Fest. ... - 2020 Nov 25
Assembly Language, Verilog HDL, Digital ECS, Analog Ciruits
Bhubaneswar, Odisha, India
... The FFT processor was designed in Verilog HDL and implemented in a FPGA. Controlling Heat Exchanger Control System July, 2018 – May, 2019 The main objectiive of the project was to design a mathematical model of heat exchanger system in SIMULINK and ... - 2019 Jun 29
... The FFT processor was designed in Verilog HDL and implemented in a FPGA. Controlling Heat Exchanger Control System July, 2018 – May, 2019 The main objectiive of the project was to design a mathematical model of heat exchanger system in SIMULINK and ... - 2019 Jun 29
Manager Design
Cuttack, Odisha, India
... ● Logic gates,Comb.Ckt.,Seq.Ckt implementation through hardware& Verilog/VHDL using Xilinx 8.1 ● VLSI lab –simulation.check syntax,synthesis through Xilinx,design of gates and comb ckt. through Microwind ● Design and Simulation through EdwinXP ● ... - 2018 Sep 06
... ● Logic gates,Comb.Ckt.,Seq.Ckt implementation through hardware& Verilog/VHDL using Xilinx 8.1 ● VLSI lab –simulation.check syntax,synthesis through Xilinx,design of gates and comb ckt. through Microwind ● Design and Simulation through EdwinXP ● ... - 2018 Sep 06
Design Engineer_Good knowledge in Verilog and SV
Bhubaneswar, Odisha, India
... VHDL and Verilog HDL 3. System Verilog 4. Hardware design using FPGA 5. C and CPP 6. Test and Debugging of the FPGA hardware board 7. Power section design 8. SI/PDN Analysis WORK EXPERIENCES 1. CSM Technologies: Worked as Jr. Network Security Expert ... - 2018 Aug 20
... VHDL and Verilog HDL 3. System Verilog 4. Hardware design using FPGA 5. C and CPP 6. Test and Debugging of the FPGA hardware board 7. Power section design 8. SI/PDN Analysis WORK EXPERIENCES 1. CSM Technologies: Worked as Jr. Network Security Expert ... - 2018 Aug 20
Project Engineer
Bhubaneswar, OD, India
... Programming Languages C, C++, VHDL, Verilog, SV, UVM, ALP. Area of Interest VLSI Design & Testing. Simulation Tools Questa Sim, Cadence, Xilinx. Work Experience: Working as an Engineer at ADE (Flight Control Computer Division), Bangalore. From 02/11 ... - 2017 Apr 19
... Programming Languages C, C++, VHDL, Verilog, SV, UVM, ALP. Area of Interest VLSI Design & Testing. Simulation Tools Questa Sim, Cadence, Xilinx. Work Experience: Working as an Engineer at ADE (Flight Control Computer Division), Bangalore. From 02/11 ... - 2017 Apr 19
Project Power
OD, 753001, India
... Skill Set: C program VHDL VERILOG PERL scripting Static Timing Analysis DFT Publications: Published a Paper in IOSR (International Organization of Scientific Research) journal under the title “Design and Implementation of Flash ADC for Low Power ... - 2016 Aug 11
... Skill Set: C program VHDL VERILOG PERL scripting Static Timing Analysis DFT Publications: Published a Paper in IOSR (International Organization of Scientific Research) journal under the title “Design and Implementation of Flash ADC for Low Power ... - 2016 Aug 11