| Resume alert | Resumes 1 - 10 of 424 |
Software Engineer Embedded
San Jose, CA
... Familiar with Verilog-HDL, synthesis, timing and logic verification. Much experience of C/C++ based embedded code development for SoC-level verification. Highlight • SoC level module integration and verification. Developed and maintained the test ... - Apr 23
... Familiar with Verilog-HDL, synthesis, timing and logic verification. Much experience of C/C++ based embedded code development for SoC-level verification. Highlight • SoC level module integration and verification. Developed and maintained the test ... - Apr 23
Ux Ui Designer
Pleasanton, CA
... Composition Color Theory, Heuristic Evaluation, Journey mapping, Presentations, Typography, Iconography, Storyboarding, Insight Synthesis, User Flow Diagrams, Usability testing, A/B testing, Site Map, Card Sorting, Stakeholder Interviews, Mockups, ... - Apr 03
... Composition Color Theory, Heuristic Evaluation, Journey mapping, Presentations, Typography, Iconography, Storyboarding, Insight Synthesis, User Flow Diagrams, Usability testing, A/B testing, Site Map, Card Sorting, Stakeholder Interviews, Mockups, ... - Apr 03
Palo Alto Litigation Support
Santa Clara, CA
... • Customized vendor tools of 10+ different EDA products from data entry, synthesis, to simulation. Senior Software Engineer 1991 - 1995 National Semiconductor Corp. (Sunnyvale) • Developed Design Automation tools for digital circuit design and ASIC ... - Apr 03
... • Customized vendor tools of 10+ different EDA products from data entry, synthesis, to simulation. Senior Software Engineer 1991 - 1995 National Semiconductor Corp. (Sunnyvale) • Developed Design Automation tools for digital circuit design and ASIC ... - Apr 03
Quality Systems Biomedical Engineering
Milpitas, CA
... • Developed the implemented software pipeline from Python that allows the synthesis of arbitrary toroidal shapes to expand the application of DNA origami technology. • Constructed scaffold routing with an unknotted pattern for the toroidal (donut ... - Mar 17
... • Developed the implemented software pipeline from Python that allows the synthesis of arbitrary toroidal shapes to expand the application of DNA origami technology. • Constructed scaffold routing with an unknotted pattern for the toroidal (donut ... - Mar 17
Front End Field Engineering
Sunnyvale, CA
... architectural co-design cutting edge AI processors Proven track record of AI processor silicon tape-out and streamlined logic synthesis, place and route, Fusion RTL, physical-aware multi-hierarchy, low-power ASIC synthesis, floor-planning, scan-DFT, ... - Mar 10
... architectural co-design cutting edge AI processors Proven track record of AI processor silicon tape-out and streamlined logic synthesis, place and route, Fusion RTL, physical-aware multi-hierarchy, low-power ASIC synthesis, floor-planning, scan-DFT, ... - Mar 10
Machine Learning Data Science
Fremont, CA
... • Conducted in-depth analysis of solar data from forecasting (HRRR) and reanalysis (ERA5) sources using AWS • Evaluated data synthesis quality metrics for energy modeling Data Science Intern May 2020 – Jul 2020 The National Center for Atmospheric ... - Feb 22
... • Conducted in-depth analysis of solar data from forecasting (HRRR) and reanalysis (ERA5) sources using AWS • Evaluated data synthesis quality metrics for energy modeling Data Science Intern May 2020 – Jul 2020 The National Center for Atmospheric ... - Feb 22
Research Scientist Postdoctoral Associate
Stanford, CA
... Teaching of "RNA extraction, cDNA synthesis, and Real-time RT-PCR" for 5 Ph.D students at the Iran University of Medical Sciences, Tehran, Iran, on Apr 2019 2. Teaching of "RNA extraction, cDNA synthesis, and Real-time RT-PCR" for 5 Ph.D students at ... - Feb 09
... Teaching of "RNA extraction, cDNA synthesis, and Real-time RT-PCR" for 5 Ph.D students at the Iran University of Medical Sciences, Tehran, Iran, on Apr 2019 2. Teaching of "RNA extraction, cDNA synthesis, and Real-time RT-PCR" for 5 Ph.D students at ... - Feb 09
Verification Engineer Fpga Design
Santa Clara, CA, 95050
... Familiar with verification plan and coverage metrics Familiar with OOP constructs and constraint random verification 10+ years of experience with FPGA design and implementation, including verification, synthesis and P&R, STA, timing analysis and ... - Feb 06
... Familiar with verification plan and coverage metrics Familiar with OOP constructs and constraint random verification 10+ years of experience with FPGA design and implementation, including verification, synthesis and P&R, STA, timing analysis and ... - Feb 06
Senior Manager Project Management
San Jose, CA
... Reid, "Cluster Synthesis and Trench Filling Using Inert Gas Condensation and Ballistic Deposition," in Advanced Metallizations for ULSI Applications in 1995, R.C. Ellwanger and Shi-Quing Wang, eds. Materials Research Society, Pittsburgh, PA, pp. 181 ... - 2023 Dec 18
... Reid, "Cluster Synthesis and Trench Filling Using Inert Gas Condensation and Ballistic Deposition," in Advanced Metallizations for ULSI Applications in 1995, R.C. Ellwanger and Shi-Quing Wang, eds. Materials Research Society, Pittsburgh, PA, pp. 181 ... - 2023 Dec 18
Design Engineer Rtl
San Jose, CA, 95118
... AES crypto block, DMA) Developed RTL for the Phy layer PCIe3.1 (PMA serdes): clock and data recovery Verified Low Power Design using MVSIM, MVRC (SNPS), and Conformal LP (CDNS), wrote UPF scripts for the low power verification and synthesis. ... - 2023 Oct 31
... AES crypto block, DMA) Developed RTL for the Phy layer PCIe3.1 (PMA serdes): clock and data recovery Verified Low Power Design using MVSIM, MVRC (SNPS), and Conformal LP (CDNS), wrote UPF scripts for the low power verification and synthesis. ... - 2023 Oct 31