| Resume alert | Resumes 11 - 20 of 56 |
Senior HR executive
Pune, Maharashtra, India
... Project: Microcontroller using VLSI coding Objective: To make inbuilt codes in microcontroller Description: Made codes using xillinx software and implemented on fpga. WORKSHOPS / CERTIFICATIONS/ SEMINARS Represented Meghalaya as venue coordinator in ... - 2021 Jan 05
... Project: Microcontroller using VLSI coding Objective: To make inbuilt codes in microcontroller Description: Made codes using xillinx software and implemented on fpga. WORKSHOPS / CERTIFICATIONS/ SEMINARS Represented Meghalaya as venue coordinator in ... - 2021 Jan 05
Engineering Design
Pune, Maharashtra, India
VIDHYACHARAN B WATHORE adi0op@r.postjobfree.com 787-***-**** AT.PO.BRAHMANGAON TAH UMARKHED DIST YAVATMAL PIN CODE:445206 Vidhyacharan wathore vidhyacharan52 Skills HDLs :VHDL, Verilog, System- Verilog, FPGA,Tanner EDA Tools:Software Modelsim, ... - 2020 Dec 29
VIDHYACHARAN B WATHORE adi0op@r.postjobfree.com 787-***-**** AT.PO.BRAHMANGAON TAH UMARKHED DIST YAVATMAL PIN CODE:445206 Vidhyacharan wathore vidhyacharan52 Skills HDLs :VHDL, Verilog, System- Verilog, FPGA,Tanner EDA Tools:Software Modelsim, ... - 2020 Dec 29
Design Engineer Power
Pune, Maharashtra, India
... Responsibility: Responsible for making ASIC RTL compatible to FPGA. Onchip Debugging using ChipscopePro. Project Undertaken In Tata Power SED: PCIe based Radar Video Acquisition Card Responsible for designing, testing and deployment of PCIe x1 Gen 1 ... - 2020 Nov 04
... Responsibility: Responsible for making ASIC RTL compatible to FPGA. Onchip Debugging using ChipscopePro. Project Undertaken In Tata Power SED: PCIe based Radar Video Acquisition Card Responsible for designing, testing and deployment of PCIe x1 Gen 1 ... - 2020 Nov 04
Engineering Details
Pune, Maharashtra, India
... C-Programming Project and Presentation Obstacle Avoidance Car using FPGA Details: The implementation on a Field Programmable Gate Array (FPGA)-Based autonomous obstacle avoidance car. The ultrasonic system mounted on a system performs the obstacle ... - 2020 Oct 09
... C-Programming Project and Presentation Obstacle Avoidance Car using FPGA Details: The implementation on a Field Programmable Gate Array (FPGA)-Based autonomous obstacle avoidance car. The ultrasonic system mounted on a system performs the obstacle ... - 2020 Oct 09
Software Engineer Data
Pune, Maharashtra, India
... Surveillance System- an FPGA based design 2. Design of a Smart Bumper System SCHOLASTIC ACHIEVEMENTS 1. Achieved a State scholarship for state rank 19th in order of merit in class four final examination. 2. Attended a science conference – DST ... - 2020 Jan 13
... Surveillance System- an FPGA based design 2. Design of a Smart Bumper System SCHOLASTIC ACHIEVEMENTS 1. Achieved a State scholarship for state rank 19th in order of merit in class four final examination. 2. Attended a science conference – DST ... - 2020 Jan 13
Verilog, FPGA design, Cadence Virtuoso, C language, Embedded C
Pune, Maharashtra, India
... Tech (Sem III & IV) : Title: Fast, Energy Efficient Approximate Multiplier Using Carry Maskable Adder and its FPGA Implementation Duration: 12 months Tool used: Xilinx ISE 14.7 Design Suite, FPGA (Spartan 3E) kit Description: Approximate ... - 2019 Dec 21
... Tech (Sem III & IV) : Title: Fast, Energy Efficient Approximate Multiplier Using Carry Maskable Adder and its FPGA Implementation Duration: 12 months Tool used: Xilinx ISE 14.7 Design Suite, FPGA (Spartan 3E) kit Description: Approximate ... - 2019 Dec 21
Python Engineering
Pune, Maharashtra, India
... • FPGA implementation of a 512Mb, 200Hz DDR SDRAM Data controller. An optimized controller was designed and implemented on FPGA. Implementation has been done in Verilog HDL using Modelsim and Xilinx ISE. • Android application on museum guide using ... - 2019 Sep 20
... • FPGA implementation of a 512Mb, 200Hz DDR SDRAM Data controller. An optimized controller was designed and implemented on FPGA. Implementation has been done in Verilog HDL using Modelsim and Xilinx ISE. • Android application on museum guide using ... - 2019 Sep 20
Manager Sales
Pune, Maharashtra, India
... Hardware Designing : ASIC, VLSI, FPGA, RF, CMOS, ASP, DSP. Engineering : CATIA, UNIGRAPHICS, NASTRAN, PATRAN, ENOVIA, IDEAS, AUTOCAD, HYPERMESH, LS-DYNA, ANSYS, WINDCHILL, PRO-E, WILDFIRE, TEAMCENTER, CREO, CFD Others : LOTUS NOTES, RETEK, CRAMER, ... - 2019 Aug 11
... Hardware Designing : ASIC, VLSI, FPGA, RF, CMOS, ASP, DSP. Engineering : CATIA, UNIGRAPHICS, NASTRAN, PATRAN, ENOVIA, IDEAS, AUTOCAD, HYPERMESH, LS-DYNA, ANSYS, WINDCHILL, PRO-E, WILDFIRE, TEAMCENTER, CREO, CFD Others : LOTUS NOTES, RETEK, CRAMER, ... - 2019 Aug 11
Electrical Project
Pune, Maharashtra, India
... Participated in FPGA Based Drive Control training program. 1 Month Training of Electrical Automation in Electro Dreams Tech Participated in Theory-Cum-Practice oriented training program on Thermal Utilities. Participated in the National Convention ... - 2019 Mar 10
... Participated in FPGA Based Drive Control training program. 1 Month Training of Electrical Automation in Electro Dreams Tech Participated in Theory-Cum-Practice oriented training program on Thermal Utilities. Participated in the National Convention ... - 2019 Mar 10
Hardware Design
Pune, MH, India
... Also worked on Xilinx and Altera FPGA’s and CPLD’s based designs, Power management, Signal Integrity and Multilayer board stack-up design. Current employment: Senior Project Lead, NEC (Dec 2014 – till date) Technical Expertise Experience in Design ... - 2018 Feb 12
... Also worked on Xilinx and Altera FPGA’s and CPLD’s based designs, Power management, Signal Integrity and Multilayer board stack-up design. Current employment: Senior Project Lead, NEC (Dec 2014 – till date) Technical Expertise Experience in Design ... - 2018 Feb 12