| Resume alert | Resumes 1 - 6 of 6 |
Software Engineer Node Js
Lehi, UT
... Updated the c/c++ code base to add fpga and multi core hardware emulation. Reduced manual testing time by architecting a C# multithreaded HTML validation tool. Debugged issues in XSLT process in C#. Designed a tool to display multiple languages of a ... - 2023 Oct 06
... Updated the c/c++ code base to add fpga and multi core hardware emulation. Reduced manual testing time by architecting a C# multithreaded HTML validation tool. Debugged issues in XSLT process in C#. Designed a tool to display multiple languages of a ... - 2023 Oct 06
Engineer
Draper, UT
... and Schematics - LinkedIn PLC Program Flow and Control Instructions - LinkedIn Learning Arduino: Foundations - LinkedIn Learning FPGA Development - LinkedIn C Programming for Embedded Applications - LinkedIn PLC Memory Organization - LinkedIn Data ... - 2021 Jun 25
... and Schematics - LinkedIn PLC Program Flow and Control Instructions - LinkedIn Learning Arduino: Foundations - LinkedIn Learning FPGA Development - LinkedIn C Programming for Embedded Applications - LinkedIn PLC Memory Organization - LinkedIn Data ... - 2021 Jun 25
Design Engineer Engineering
Provo, UT
... 2002 present Brigham Young University, Provo, UT o PhD Computer Engineering April 2011 o Research Emphasis: Reliable Digital Communications on FPGAs o Dissertation: Analysis and Mitigation of SEU-induced Noise in FPGA-based DSP Systems o Graduate ... - 2013 Feb 03
... 2002 present Brigham Young University, Provo, UT o PhD Computer Engineering April 2011 o Research Emphasis: Reliable Digital Communications on FPGAs o Dissertation: Analysis and Mitigation of SEU-induced Noise in FPGA-based DSP Systems o Graduate ... - 2013 Feb 03
Power Energy
Provo, UT
Reducing Energy in FPGA Multipliers Through Glitch Reduction Nathaniel Rollins and Michael J. Wirthlin, abqatz@r.postjobfree.com, and abqatz@r.postjobfree.com Department of Electrical and Computer Engineering Brigham Young University, Provo, UT. ... - 2013 Jan 31
Reducing Energy in FPGA Multipliers Through Glitch Reduction Nathaniel Rollins and Michael J. Wirthlin, abqatz@r.postjobfree.com, and abqatz@r.postjobfree.com Department of Electrical and Computer Engineering Brigham Young University, Provo, UT. ... - 2013 Jan 31
Quality Assurance Management
West Jordan, UT, 84088
... Sandy, UT COO (2007) Secured newly acquired Realm Systems indentity management technology, including advanced FPGA-powered hardware and Linux-based operating system. Implemented low-cost hardware and software development efforts to refine prototypes ... - 2012 Jul 25
... Sandy, UT COO (2007) Secured newly acquired Realm Systems indentity management technology, including advanced FPGA-powered hardware and Linux-based operating system. Implemented low-cost hardware and software development efforts to refine prototypes ... - 2012 Jul 25
Signal Processing Assistant
Provo, UT, 84606
... • Development of Real-time Digital Backend for the Phased Array Feeds using FPGA-based ROACH boards and CASPER libraries. This includes developing of real-time 64-channel spectrometer, beam former and correlator & streaming the processed data over ... - 2012 May 18
... • Development of Real-time Digital Backend for the Phased Array Feeds using FPGA-based ROACH boards and CASPER libraries. This includes developing of real-time 64-channel spectrometer, beam former and correlator & streaming the processed data over ... - 2012 May 18