| Resume alert | Resumes 1 - 10 of 12 |
CFO
Singapore, Central, Singapore
... to a Global Media Group q Setting up their policies and procedures including multiple country legal entity setups and reporting cadence q Assisting with HR in the absence of an HR Director Nov18 – Now VADN Group – Director (Singapore) – Strategy & ... - 2022 Mar 31
... to a Global Media Group q Setting up their policies and procedures including multiple country legal entity setups and reporting cadence q Assisting with HR in the absence of an HR Director Nov18 – Now VADN Group – Director (Singapore) – Strategy & ... - 2022 Mar 31
Physical Design Engineer
Singapore, Central Region, Singapore
... Proficient in using Cadence tools (Virtuoso, Composer, Calibre). Making schedule to complete tasks ahead the deadline. Working experience on 130nm, 65nm and 55nm. DOAN NHAT THIEN ADDRESS: 04-152, block 111, Bishan street 12, Singapore 570111 PHONE: ... - 2020 Feb 27
... Proficient in using Cadence tools (Virtuoso, Composer, Calibre). Making schedule to complete tasks ahead the deadline. Working experience on 130nm, 65nm and 55nm. DOAN NHAT THIEN ADDRESS: 04-152, block 111, Bishan street 12, Singapore 570111 PHONE: ... - 2020 Feb 27
Sales Management
Singapore
... Peak Performing Teams – Repeated success in building, recruiting, coaching and mentoring sales teams with on-going performance reviews, cadence and account planning resulting in 18 out of 20 reps exceeding goals and achieving bonuses of up to $300K. ... - 2019 May 20
... Peak Performing Teams – Repeated success in building, recruiting, coaching and mentoring sales teams with on-going performance reviews, cadence and account planning resulting in 18 out of 20 reps exceeding goals and achieving bonuses of up to $300K. ... - 2019 May 20
Analog RF LAYOUT DESIGN Engineer
Woodlands, 737788, Singapore
... Scripting expertise in Cadence SKILL (P-Cell & design automation), TCL, C-shell, etc Expertise in Cadence & Mentor, Virtuoso(ICADV12, 6.1.x, 5.1.x), PVS & Calibre. Full Chip DRC, LVS verification sign off for Customer IP’s & suggestion for ... - 2019 Mar 08
... Scripting expertise in Cadence SKILL (P-Cell & design automation), TCL, C-shell, etc Expertise in Cadence & Mentor, Virtuoso(ICADV12, 6.1.x, 5.1.x), PVS & Calibre. Full Chip DRC, LVS verification sign off for Customer IP’s & suggestion for ... - 2019 Mar 08
Senior Release Project Manager
Singapore, East Region, Singapore
... maintain project success rate of 80 to 86% • Lead implementation, interface management, UAT tracking and governance activities aligning to the release cadence for EMEA • Conduct implementation and tracking of customer-facing channels such as host, ... - 2018 Sep 17
... maintain project success rate of 80 to 86% • Lead implementation, interface management, UAT tracking and governance activities aligning to the release cadence for EMEA • Conduct implementation and tracking of customer-facing channels such as host, ... - 2018 Sep 17
Engineer Manufacturing
Singapore, 320018, Singapore
... Schematic Entry Cadence : ORCAD Capture 9.0 Read and Schematic Diagrams Quality Standards ISO 9001:2008 & AS9100B, 13485 – Medical Office Excel, Power point & MS Word Educational Details: Diploma in Computer networking (1 Year) From 2013 to 2014 in ... - 2018 Jan 07
... Schematic Entry Cadence : ORCAD Capture 9.0 Read and Schematic Diagrams Quality Standards ISO 9001:2008 & AS9100B, 13485 – Medical Office Excel, Power point & MS Word Educational Details: Diploma in Computer networking (1 Year) From 2013 to 2014 in ... - 2018 Jan 07
manager
Singapore
... - Benchmark against Synopsys, Cadence, Xilinx and Altera for performance (area and speed). Achievement : Excellent Service and Performance Award in 2001 and 2002. Reason for Leaving : IC Design houses relocated to China and India. Test Specialist ... - 2016 Oct 18
... - Benchmark against Synopsys, Cadence, Xilinx and Altera for performance (area and speed). Achievement : Excellent Service and Performance Award in 2001 and 2002. Reason for Leaving : IC Design houses relocated to China and India. Test Specialist ... - 2016 Oct 18
Digital Design Verification, System verilog, UVM
Singapore
... Possess strong experience using UVM Methodology for developing verification Environment Familiar in setting up environment and doing Gate Level simulations Familiar with Synopsys and Cadence simulators and Tools In depth knowledge in FPGA, STA, DFT, ... - 2015 Mar 03
... Possess strong experience using UVM Methodology for developing verification Environment Familiar in setting up environment and doing Gate Level simulations Familiar with Synopsys and Cadence simulators and Tools In depth knowledge in FPGA, STA, DFT, ... - 2015 Mar 03
Design Engineer Project
Singapore, Singapore
... Tools: Synopsys IC Compiler, Cadence Encounter - Timing Analysis: Synopsys PrimeTime - Layout Tool: Calibre, Laker Scripting Languages - TCL - PERL - I am experienced at communicating with people from different parts of world and working with them. ... - 2015 Jan 16
... Tools: Synopsys IC Compiler, Cadence Encounter - Timing Analysis: Synopsys PrimeTime - Layout Tool: Calibre, Laker Scripting Languages - TCL - PERL - I am experienced at communicating with people from different parts of world and working with them. ... - 2015 Jan 16
Engineering Electrical
Singapore
... • RELATED SOFTWARE • Cadence, Spectre, SpectreRF, Ultrasim, Virtuoso, Virtuoso XL • Mentor Graphics Software, ADS, Matlab • H-Spice, P-Spice - 2014 Apr 08
... • RELATED SOFTWARE • Cadence, Spectre, SpectreRF, Ultrasim, Virtuoso, Virtuoso XL • Mentor Graphics Software, ADS, Matlab • H-Spice, P-Spice - 2014 Apr 08