| Resume alert | Resumes 1 - 9 of 9 |
Verilog coding
Visakhapatnam, Andhra Pradesh, India
... 2016, visakhapatnam, 65% SKILLS verilog coding basics of c programming c++ Basics of java and python commuication skills problem solving team work can work under stressed conditions basic computer knowledge time management can handle cadence,linux. ... - 2023 Sep 11
... 2016, visakhapatnam, 65% SKILLS verilog coding basics of c programming c++ Basics of java and python commuication skills problem solving team work can work under stressed conditions basic computer knowledge time management can handle cadence,linux. ... - 2023 Sep 11
Control Systems Fpga Design
Visakhapatnam, Andhra Pradesh, India
... AP 10th grade (2014) CGPA - 7.0 Specializations Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx Vivado Projects ... - 2023 Sep 11
... AP 10th grade (2014) CGPA - 7.0 Specializations Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx Vivado Projects ... - 2023 Sep 11
Air Force Project Engineer
Visakhapatnam, Andhra Pradesh, India
... Skills & Expertise Bill of Material, Cadence, Orcad & Schematics preparation. Document Preparation & Verification. In using Electronic Equipment's like CRO, DMM etc… In using of RF Equipment's like Signal Generator, Signal Analyzer, Power Meter, etc ... - 2022 May 03
... Skills & Expertise Bill of Material, Cadence, Orcad & Schematics preparation. Document Preparation & Verification. In using Electronic Equipment's like CRO, DMM etc… In using of RF Equipment's like Signal Generator, Signal Analyzer, Power Meter, etc ... - 2022 May 03
Design Assistant
Visakhapatnam, Andhra Pradesh, India
... on radix-2 modified booth encoding algorithm Tools used VHDL, Xilinx 14.6,ModelSim10.0,Cadence Hardware used: Spartan 6 FPGA Description The objective of a good multiplier is to provide a physically compact, good speed low power consuming chip. ... - 2020 Dec 14
... on radix-2 modified booth encoding algorithm Tools used VHDL, Xilinx 14.6,ModelSim10.0,Cadence Hardware used: Spartan 6 FPGA Description The objective of a good multiplier is to provide a physically compact, good speed low power consuming chip. ... - 2020 Dec 14
Air Force Engineer
Visakhapatnam, Andhra Pradesh, India
... International Paper IJARCCE (Published a research paper entitled Low Power FinFET Based Full Adder Design) Volume 6, Issue 8, August 2017 AFFILIATION SKILLS C, C++, CADENCE, DIGITAL ELECTRONICS, Verilog HDL OPERATING SYSTEMS MS Office, Access, Power ... - 2020 Jul 15
... International Paper IJARCCE (Published a research paper entitled Low Power FinFET Based Full Adder Design) Volume 6, Issue 8, August 2017 AFFILIATION SKILLS C, C++, CADENCE, DIGITAL ELECTRONICS, Verilog HDL OPERATING SYSTEMS MS Office, Access, Power ... - 2020 Jul 15
Project Technical
Visakhapatnam, Andhra Pradesh, India
... Worked on “ANALOG VLSI DESIGN” and designed a Frequency Divider by 2(or)3 in cadence as my mini-project. WORKSHOPS: Had done a workshop on “Ethical Hacking” during our college technical fest in 2016. Had done a workshop on “Internet of Things” ... - 2020 Jan 20
... Worked on “ANALOG VLSI DESIGN” and designed a Frequency Divider by 2(or)3 in cadence as my mini-project. WORKSHOPS: Had done a workshop on “Ethical Hacking” during our college technical fest in 2016. Had done a workshop on “Internet of Things” ... - 2020 Jan 20
Industrial Training
Visakhapatnam, Andhra Pradesh, India
... • Additional Skills: Proteus 8, Cadence, HTML, CSS, JavaScript, PHP, Laravel. Extra-Curricular Activities Class Representative Lovely Professional University, Punjab ECE Department 2017 - 2018 Student Coordinator Lovely Professional University, ... - 2018 Aug 18
... • Additional Skills: Proteus 8, Cadence, HTML, CSS, JavaScript, PHP, Laravel. Extra-Curricular Activities Class Representative Lovely Professional University, Punjab ECE Department 2017 - 2018 Student Coordinator Lovely Professional University, ... - 2018 Aug 18
Professional Experience High School
Visakhapatnam, 530001, India
... Technical skills: Softwares : Tanner, Xillinx, cadence. Proramming Languages : Verilog. Pre professional experience: Stood as 2nd Class Representative in 1st year. Stood as 1st Class Reprentative in 3rd year 1st semester. Elected as Students Hostel ... - 2016 Apr 28
... Technical skills: Softwares : Tanner, Xillinx, cadence. Proramming Languages : Verilog. Pre professional experience: Stood as 2nd Class Representative in 1st year. Stood as 1st Class Reprentative in 3rd year 1st semester. Elected as Students Hostel ... - 2016 Apr 28
Project Design
Visakhapatnam, 530001, India
... DESIGINING OF CAVITY FILTERS USING HFSS Good Understanding in Digital design architectures and RTL coding Good understanding of Cadence Virtuoso tool. Good knowledge of FPGA Design Flow Hardware design using Verilog. Knowledge in System Verilog. ... - 2016 Feb 23
... DESIGINING OF CAVITY FILTERS USING HFSS Good Understanding in Digital design architectures and RTL coding Good understanding of Cadence Virtuoso tool. Good knowledge of FPGA Design Flow Hardware design using Verilog. Knowledge in System Verilog. ... - 2016 Feb 23