| Resume alert | Resumes 1 - 10 of 38 |
Parent Relationship Manager
Pune, Maharashtra, India
... Diploma in Interior Designing from Cadence School of Interior and fashion designing, Nagpur. Achievements:- In 2 years of tenure got approx. 400 + new admissions by counseling and have 60% rollover conversion ratio and 65-70% walk in conversion ... - 2021 Aug 24
... Diploma in Interior Designing from Cadence School of Interior and fashion designing, Nagpur. Achievements:- In 2 years of tenure got approx. 400 + new admissions by counseling and have 60% rollover conversion ratio and 65-70% walk in conversion ... - 2021 Aug 24
Project Engineering
Pune, Maharashtra, India
... Languages: C, C++, OOP, Python, Verilog, SystemVerilog, UVM • Development and Simulation Tools: Cadence, Xilinx ISE, Orcad 99SE, Keil μVision, NGspice, Proteus, MATLAB • Worked as a Project Intern in the domain of VLSI with ESCICOMP-INDIA PVT. ... - 2021 Mar 11
... Languages: C, C++, OOP, Python, Verilog, SystemVerilog, UVM • Development and Simulation Tools: Cadence, Xilinx ISE, Orcad 99SE, Keil μVision, NGspice, Proteus, MATLAB • Worked as a Project Intern in the domain of VLSI with ESCICOMP-INDIA PVT. ... - 2021 Mar 11
Design Engineer
Pune, Maharashtra, India
... EDA Tools : Cadence (Virtuoso, NCsim, Irun), Mentor Graphics Questa Sim, Pspice, Open timer, Primetime. HDL Programming : Verilog(Xilinx ISE Design Suite). Microcontroller Programming : 8051, UART, I2C, SPI programming. Linux Programming : Basics of ... - 2021 Feb 12
... EDA Tools : Cadence (Virtuoso, NCsim, Irun), Mentor Graphics Questa Sim, Pspice, Open timer, Primetime. HDL Programming : Verilog(Xilinx ISE Design Suite). Microcontroller Programming : 8051, UART, I2C, SPI programming. Linux Programming : Basics of ... - 2021 Feb 12
Design Engineer
Pune, Maharashtra, India
... Skill Set: Tools: Cadence Encounter Digital Implementation,Cadence VIRTUOSO, Cadence Innovus. Verification : Virtuos, Caliber,Innovus. Operating Systems: Windows, Linux,Redhat. CERTIFICATIONS: MENTOR Graphics Training In (Digital Verification). VLSI ... - 2021 Feb 12
... Skill Set: Tools: Cadence Encounter Digital Implementation,Cadence VIRTUOSO, Cadence Innovus. Verification : Virtuos, Caliber,Innovus. Operating Systems: Windows, Linux,Redhat. CERTIFICATIONS: MENTOR Graphics Training In (Digital Verification). VLSI ... - 2021 Feb 12
Project Design embedded system development hardware design and PCB des
Pune, Maharashtra, India
... EDA Tools- Cadence virtuoso, LT Spice, AWR Microwave office, NI Lab-VIEW, Xilinx ISE 14.7, Proteus 8.1, 4nec2, MATLAB, Diptrace, RS Logix,HFSS. Software skills – Assembly, C, Embedded C. Platforms - Linux, Windows. IDE Tools- MPLAB X, Arduino,, Keil ... - 2021 Feb 10
... EDA Tools- Cadence virtuoso, LT Spice, AWR Microwave office, NI Lab-VIEW, Xilinx ISE 14.7, Proteus 8.1, 4nec2, MATLAB, Diptrace, RS Logix,HFSS. Software skills – Assembly, C, Embedded C. Platforms - Linux, Windows. IDE Tools- MPLAB X, Arduino,, Keil ... - 2021 Feb 10
Engineer Analyst
Pune, Maharashtra, India
... Established regular cadence of meetings with key client stakeholders to ensure alignment of program outcomes and deliverables with client’s goals Accurately assesses problems and actively played the role of intermediary between the Business & ... - 2021 Jan 12
... Established regular cadence of meetings with key client stakeholders to ensure alignment of program outcomes and deliverables with client’s goals Accurately assesses problems and actively played the role of intermediary between the Business & ... - 2021 Jan 12
PCB Design Engineer
Pune, Maharashtra, India
... Cadence Allegro V17.2 tool handling. Skilled in schematic packages. PCB workflow up to output deliverables i.e. Gerber, Stencil and other data file creation. Work on EMI/EMC concept. Handling EQ’s by providing solution. Employer: Moloch Designs ... - 2020 Nov 23
... Cadence Allegro V17.2 tool handling. Skilled in schematic packages. PCB workflow up to output deliverables i.e. Gerber, Stencil and other data file creation. Work on EMI/EMC concept. Handling EQ’s by providing solution. Employer: Moloch Designs ... - 2020 Nov 23
Design Engineer Power
Pune, Maharashtra, India
... Technical Experties: HDL Languages : Verilog, VHDL RTL Entry & Synthesis Tool : Synopsys Design Compiler, Cadence RTL Compiler. Frontend EDA Tools : SpyGlass LINT, SpyGlass CDC, Questa CDC, Synopsys Formality, Synopsys Prime Time. Backend Tool : ... - 2020 Nov 04
... Technical Experties: HDL Languages : Verilog, VHDL RTL Entry & Synthesis Tool : Synopsys Design Compiler, Cadence RTL Compiler. Frontend EDA Tools : SpyGlass LINT, SpyGlass CDC, Questa CDC, Synopsys Formality, Synopsys Prime Time. Backend Tool : ... - 2020 Nov 04
Verilog, FPGA design, Cadence Virtuoso, C language, Embedded C
Pune, Maharashtra, India
... Tech (Sem I) : Title: Layout design, DRC, LVS, Parameter Extraction and post layout simulation for CMOS Inverter and basic logic gates Duration: 4 months Tool used: Cadence Virtuoso Description: This project demonstrates the physical design, design ... - 2019 Dec 21
... Tech (Sem I) : Title: Layout design, DRC, LVS, Parameter Extraction and post layout simulation for CMOS Inverter and basic logic gates Duration: 4 months Tool used: Cadence Virtuoso Description: This project demonstrates the physical design, design ... - 2019 Dec 21
Python Marketing
Pune, Maharashtra, India
... * NATIONAL LEVEL WORKSHOP ON “VLSI CADENCE TOOL” AT DEPARTMENT OF ELECTRONICS, KBC NORTH MAHARASHTRA UNIVERSITY, JALGAON (MAHARASHTRA) * STATE LEVEL WORKSHOP ON “PYTHON PROGRAMMING” IN KAVERI COLLEGE OF ARTS, SCIENCE AND COMMERCE PUNE - 2019 Dec 18
... * NATIONAL LEVEL WORKSHOP ON “VLSI CADENCE TOOL” AT DEPARTMENT OF ELECTRONICS, KBC NORTH MAHARASHTRA UNIVERSITY, JALGAON (MAHARASHTRA) * STATE LEVEL WORKSHOP ON “PYTHON PROGRAMMING” IN KAVERI COLLEGE OF ARTS, SCIENCE AND COMMERCE PUNE - 2019 Dec 18