| Resume alert | Resumes 1 - 7 of 7 |
IT Operation Management & Services
Ahmedabad, Gujarat, India
... Ownership of preparing MBR, QBR and Cadence reports with 100% accuracy and demonstrate with clients. Desktop, Laptops, Thin Clients, IP Phones, Headset or other assets which required to run the operation without any disruption needs to be taken care ... - 2020 Jul 21
... Ownership of preparing MBR, QBR and Cadence reports with 100% accuracy and demonstrate with clients. Desktop, Laptops, Thin Clients, IP Phones, Headset or other assets which required to run the operation without any disruption needs to be taken care ... - 2020 Jul 21
VLSI, VHDL, LABVIEW
Gandhinagar, GJ, 382010, India
... Programming Languages: C, C++, Java, Embedded C, Assembly Language, VHDL, Verilog, DBMS Software knowledge: MAT LAB, Computer Simulation Technology, ORCAD, Mentor Graphics, XILINX, LabVIEW (Core I and Core II), Altera, Cadence (beginner) SUBJECT ... - 2016 Jun 27
... Programming Languages: C, C++, Java, Embedded C, Assembly Language, VHDL, Verilog, DBMS Software knowledge: MAT LAB, Computer Simulation Technology, ORCAD, Mentor Graphics, XILINX, LabVIEW (Core I and Core II), Altera, Cadence (beginner) SUBJECT ... - 2016 Jun 27
Please find the attached CV in response to the EC/ VLSI/ASIC/ FPGA Job
Ahmedabad, GJ, India
... Design Tools & software’s : Modelsim, Questasim, Mentor Graphics, Xilinx, Altera Quatrus II, Cadence, Knowledge of Linux, Arudino,Virtual Hardware design using Proteus Software. Microcontrollers : 8051. AREA OF INTEREST VLSI Data communication and ... - 2016 Jun 18
... Design Tools & software’s : Modelsim, Questasim, Mentor Graphics, Xilinx, Altera Quatrus II, Cadence, Knowledge of Linux, Arudino,Virtual Hardware design using Proteus Software. Microcontrollers : 8051. AREA OF INTEREST VLSI Data communication and ... - 2016 Jun 18
Professional Experience ASIC Verification Domain
Ahmedabad, GJ, India
... Designing is done in Verilog and simulation is done in Cadence tool. Verification is done in System Verilog using CRV (Constrained Random Verification) methodology. M-Tech Project: HDLC CONTROLLER DESIGN: Designed HDLC transmitter using Verilog HDL, ... - 2016 Mar 22
... Designing is done in Verilog and simulation is done in Cadence tool. Verification is done in System Verilog using CRV (Constrained Random Verification) methodology. M-Tech Project: HDLC CONTROLLER DESIGN: Designed HDLC transmitter using Verilog HDL, ... - 2016 Mar 22
Electronics design Engineer
Ahmedabad, GJ, India
... TOOLS AND LANGUAGE SKILLS Programming languages: C and C++ (basic) HDL: VHDL and VERILOG (basic coding) Cadence tools: Virtuoso Layout Editor, Schematic Composer, Spectre Environment, DRC, LVS Board Design Tool: ModelSim (Altera) VHDL Simulation: ... - 2014 Oct 13
... TOOLS AND LANGUAGE SKILLS Programming languages: C and C++ (basic) HDL: VHDL and VERILOG (basic coding) Cadence tools: Virtuoso Layout Editor, Schematic Composer, Spectre Environment, DRC, LVS Board Design Tool: ModelSim (Altera) VHDL Simulation: ... - 2014 Oct 13
Engineer Server
Ahmedabad, GJ, 380016, India
... Install and Maintain EDA tools e.g.- Cadence, Mentor, Synopsys etc.. . Install and Maintain EDA License and Vendore Daemon . Administration of Vmware Server ( Esxi3.5 / ESXi4 / ESXi5 ) . Administration of Linux Mail Server . Responsible for critical ... - 2013 Jun 07
... Install and Maintain EDA tools e.g.- Cadence, Mentor, Synopsys etc.. . Install and Maintain EDA License and Vendore Daemon . Administration of Vmware Server ( Esxi3.5 / ESXi4 / ESXi5 ) . Administration of Linux Mail Server . Responsible for critical ... - 2013 Jun 07
Engineer Assistant
Gandhinagar, GJ, 382007, India
... Xavier’s, Gandhinagar (Gujarat) 10th (GSEB) - 85.43% Skills Expertise Area VLSI subsystem Design, Analog circuit design Programming Language C, Verilog HDL, VHDL Tools and Technologies Cadence Virtuoso, Xilinx ISE, Lt Spice, Multisim, Modelsim, ... - 2012 Aug 29
... Xavier’s, Gandhinagar (Gujarat) 10th (GSEB) - 85.43% Skills Expertise Area VLSI subsystem Design, Analog circuit design Programming Language C, Verilog HDL, VHDL Tools and Technologies Cadence Virtuoso, Xilinx ISE, Lt Spice, Multisim, Modelsim, ... - 2012 Aug 29