| Job alert | Jobs 1 - 10 of 150 |
DFT Engineer (SoC product development)
ATR International
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Milpitas, CA
... · Strong knowledge of DFT methodologies, industrial standards, and practices · Strong working knowledge of Chip design, Verilog/System Verilog, and design verification · Experience with STA tools like Primetime, SDF generation and Gate-level ... - Apr 02
Automation/Controls Engineer
SIX SIGMA/Winslow Automation Inc.
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Milpitas, CA, 95035
... Familiarity with low-level programming languages such as C, Rust, Verilog, or any assembly language. Familiarity with programmable logic controllers (PLCs) or programmable automation controllers (PACs) and their programming languages (ladder logic, ... - Apr 11
FPGA Verification Engineer
Arista Networks
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Santa Clara, CA
... Job Responsibilities: Create and maintain test benches in Verilog/SystemVerilog Create BFM, RTL models for new and existing designs Develop the verification test plans and test cases Review the design functional coverage Concepts and Skills: Data ... - Apr 09
Senior ASIC Design Engineer
ATR International
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Milpitas, CA
... crossings Integration of IPs/modules/sub-systems designed by internal/external teams Experience using AMBA bus protocols System Verilog experience Lint and CDC execution and analysis writing timing constraints and timing analysis Technical document ... - Apr 02
Accelerator Verification Engineer
Ursus, Inc.
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Santa Clara, CA, 95053
... Expertise in System Verilog / C++ / Python . Ability to work in a fast paced environment and deliver results. - Apr 14
RTL Design Engineer
LanceSoft, Inc.
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San Jose, CA
... PREFERRED EXPERIENCE: • 10 years' experience in RTL coding • Knowledge of PCIe Gen5 and PIPE specification • Knowledge of ASIC development flows • Knowledge of system verilog • Multi-clock domain designs. • Design constraints for synthesis and ... - Apr 17
RTL Design Engineer - Senior
US Tech Solutions
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San Jose, CA
... Responsibilities: Knowledge of PCIe Gen5 and PIPE specification Knowledge of ASIC development flows Knowledge of system verilog Multi-clock domain designs. Design constraints for synthesis and static timing analysis. Experience: 10+ years of ... - Apr 10
Senior Digital Design Engineer
Ethan Alexander Group
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Santa Clara, CA
... Requirement Document (PRD) Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL Developing standalone testbenches to verify the RTL behavior Writing and verifying ... - Apr 11
Senior ASIC Verification Engineer San Jose On-Site Excellent
Orbis Group
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San Jose, CA
... hierarchy, Cache coherency, Virtual memory, Multicore CPU operation • Familiarity with AMBA/APB/AXI Protocol • Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C • Excellent Verilog/System Verilog programming skills. ... - Apr 15
ASIC Design Engineer
TCWGlobal
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San Jose, CA
... JOB Requirements Strong Experience in RTL design, design verification, synthesis (Genus experience strongly preferred) & formal verification Strong Experience in Tempus and Verilog simulation tools Strong Experience in LINT, CDC, and RDC (SpyGlass ... - Apr 19