| Job alert | Jobs 51 - 60 of 443 |
ACL Digital - Senior Design Verification Engineer - UVM/C++
ACL Digital
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Bangalore, Karnataka, India
... level verification - Hands on experience with assembly, UVM, SV, C++ - Experience in developing complex test bench/model in UVM, Verilog, System Verilog - Hands on experience in developing test plans, coverage closure - Ability to code readable, ... - Apr 25
Field-Programmable Gate Arrays Engineer
Tonbo Imaging
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Bengaluru, Karnataka, India
... Proven experience in FPGA design and development, including VHDL or Verilog programming. Strong understanding of digital signal processing (DSP) concepts and algorithms. Hands-on experience with FPGA development tools and platforms (e.g., Xilinx ... - Apr 23
RF Digital Design Engineer
QpiAI
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VasanthaNagar, Karnataka, 560001, India
... ● Understanding of RTL coding with Verilog, Module level functional simulation, verification and synthesis. ● Hands-on experience with FPGA prototyping with toolset and process flow of FPGAs from Xilinx Vivado, Vitis or Altera. ● Knowledge of ... - Apr 05
Member Technical Staff
Maven Silicon
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VasanthaNagar, Karnataka, 560001, India
Extensive hands on and teaching experience on Digital/SV/UVM/Verilog/VHDL /DFT tools Experience on Mentor Graphics EDA flow/Cadence Tool/Synopsys Tool is an added advantage Responsible for development and support of Projects. Responsible for ... - Mar 29
Infra Systems Architect - Engineer Staff
Qualcomm Technologies, Inc
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VasanthaNagar, Karnataka, 560001, India
... arch evolution) Good communication and work with minimal supervision Collaborate with Perf, Design and System team stakeholders in developing solutions Experience with Verilog, logic design principles with timing, area and power implications. ... - Mar 29
Senior RTL Design Engineer
ACL Digital
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VasanthaNagar, Karnataka, 560001, India
... Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. 3. Should have experience using ASIC ... - Mar 29
Senior Lead Design Engineer, RTL And Front-End Design
L&T Semiconductor Technologies
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Bengaluru, Karnataka, India
... Experience and knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus. Proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and ... - Apr 20
RTL (FPGA Design)
Alp Consulting Ltd.
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VasanthaNagar, Karnataka, 560001, India
... • Experience with Xilinx/Intel (Altera) • Familiarity with high level programming languages like C/C++, System Verilog, Scripts (TCL, Python) – advantage • Experience with UVM verification flow – advantage. - Apr 01
Analog Circuit Design
ACL Digital
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VasanthaNagar, Karnataka, 560001, India
... Any RTL language (verilog, VHDL) will have additional preferrrance. 6. Candidates with system modeling experience, power delivery networks, Signal Integrity and Power Integrity experiences can also apply. 7. Candidate is necessarily required to have ... - Mar 28
R&D Engineering, Sr Engineer
Synopsys
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VasanthaNagar, Karnataka, 560001, India
... Knowledge on Verilog, VHDL or other HDL languages would be plus. Full time - Apr 19