DFT (Design for Test) Engineer 3

Job Description

seeking a DFT (Design for Test) Engineer 3 for a contract/remote opportunity.

BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE):

o Bachelor's degree in Electrical or Computer Engineering with 8 years of experience, a Master's degree with 6 years of experience.

o U.S. Citizenship is required.

o Experience in full product life cycle of ASIC Design.

o Experience with Cadence and/or Mentor test insertion and ATPG tools.

o Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG).

o Experience with memory BIST and logic BIST.

o Experience generating test patterns and analyzing and debugging test failures.

o Experience working with test engineers to implement ATPG vectors on tester hardware.

o Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl.

o Effective communication and presentation skills and high proficiency in technical problem solving.

POSITION RESPONSIBILITIES:

Looking for a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.

Responsibilities:

o Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts.

o Adhering to ASIC development process.

o Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies.

o Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.

PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE):

o Master's Degree in Electrical or Computer Engineering.

o Expertise of using Cadence Modus DFT tools.

o Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus.

REQUIRED EDUCATION:

Bachelor's degree in Electrical or Computer Engineering is required.

School must be accredited.

HOURS:

9/80 workweek. Remote position.

Full-time

Fully remote