Senior PLL Engineer
Description:
Senior PLL Design Engineer
Location: Aachen Full-time Semiconductor Industry
A well-funded deep-tech semiconductor company is seeking a Senior PLL Design Engineer to join its analog/mixed-signal team. You’ll design and verify high-performance Phase-Locked Loops (PLLs) for SoC and mixed-signal applications where you work will directly impact the success of their silicon products across a range of advanced nodes.
Key Responsibilities:
Design PLL building blocks: VCOs, charge pumps, PFDs, loop filters, dividers
Perform transistor-level and behavioral simulations (Spectre, HSPICE, Verilog-A/AMS)
Optimize for jitter, power, and area
Work closely with layout, digital, and verification teams
Support silicon validation and SoC integration
Your Profile:
M.Sc. or Ph.D. in Electrical Engineering
Strong experience in PLLs, clocking, or high-speed analog/mixed-signal design
Solid understanding of jitter/noise modeling and analog fundamentals
Proficient with Cadence tools and modern CMOS nodes
Team-oriented with strong communication skills
Why Join:
Shape cutting-edge silicon at a high-growth semiconductor innovator
Work on next-gen analog IP in an expert, collaborative environment
Interested to know more?
Apply here with your CV .
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