Senior FPGA Firmware Engineer (Contract)

Senior FPGA Firmware Engineer (Job Location: El Segundo, CA area, about15 miles south-east of Los Angeles) Job Summary Client is seeking a Senior FPGA Firmware Engineer with expertise in digital signal processing, coherent combining of digital signals, high-bandwidth networking, and VITA 49.

In this role, you will design, develop, and optimize FPGA-based solutions using Xilinx High-Level Synthesis (HLS) using C++. Essential Job Duties and Responsibilities Develop coherent combining and beamforming modules using C++ and Xilinx HLS, ensuring precise phase alignment across multiple channels.

Requirements capturing, design definition & implementation of VHDL detailed designs Implement VITA 49-compliant data packetization for high-speed IF or RF data distribution.

Design and fine-tune DSP blocks (e.g., FFT, filtering, NCO, cross-correlation) to meet stringent real-time and resource utilization requirements.

Work closely with cross-functional teams to ensure signal integrity and minimize latency in large-scale, multi-channel systems.

Use Vivado (or Vitis) for synthesis, simulation, timing closure, and debug.

Create testbenches in C++/System Verilog/Python to validate functional correctness and phase coherence across all channels.

Provide guidance to junior engineers, reviewing design approaches and ensuring best practices for coherent signal processing.

Collaborate with firmware, software, and hardware teams to define project requirements and deliver high-quality solutions on schedule.

Skills and/or Experience Needed: *KeySkills: FPGA PROGRAMMING, PYTHON, C++, VIVADO, IDE, LINUX MS or BS in Electrical Engineering, Computer Engineering, or related field, or related engineering field 5+ years of professional experience in FPGA development, specifically in signal processing and high-speed I/O.

Proven expertise with Xilinx HLS (Vivado / Vitis), writing performance-critical C++ for FPGA synthesis.

Hands-on experience with coherent combining, beamforming, or similar multi-channel synchronization techniques.

Strong knowledge of VITA 49, including metadata handling and packet-based transport of digitized signals.

Knowledge of Software-Defined Radio (SDR) is a plus Experience with Xilinx RFSoC is a plus Proficiency in VHDL/Verilog and FPGA design methodologies Experience with Vivado Design Suite and Xilinx SDK Familiarity with high-bandwidth networking protocols (Ethernet up to 100Gb, PCIe, or similar). Solid grasp of digital signal processing fundamentals (filters, FFTs, channelization, interference cancellation). Proficiency in FPGA development flows (Vivado, ModelSim, or similar) and lab debugging (ILAs, scopes). Excellent communication and collaboration skills.

Soft Skills Polished interpersonal skills and presentation skills.

Additional Skills/Experience that would be a “plus” (not required): Advanced degree (MSEE/PhD) with a focus on DSP, Communications, or FPGA acceleration Preferred Experience with additional standards/protocols relevant to software-defined radio or phased-array systems preferred Familiarity with scripting languages (Python, TCL) for automation and testing highly desirable Track record of publishing or patenting innovations in signal processing or hardware acceleration highly desirable Additional Requirements US Citizenship or lawful permanent residence in the U.S.

required in support of US Government contracts/subcontracts