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Senior Design Verification Engineer

Royce Ashland Group, Inc.
Sunnyvale, California, United States
July 25, 2018


The FPGA Design Verification Engineer, will support the DNA Sequencing unit, you will be responsible for all aspects of the verification of FPGA designs and will contribute to the verification of ASIC designs, including block-level and chip-level functional test plan development, test bench and model’s creation, detailed verification of every aspect of the chip functionality. In addition, you will engage in other aspects of design verification, including front-end architecture planning, system modeling, external IP integration verification, flow development, and EDA tool evaluation and selection.


• Ownership of all aspects of the design verification of the FPGA chips and/or its functional blocks

• Test Plan ownership, and coordination with Architecture, Design, DFT, and other teams to deliver a complete, comprehensive verification plan

• Ownership of system, chip, and IP models for verification

• Evaluation and selection of flows and EDA tools

• Development and deployment of processes and flows for Design Verification


• A Master or BS degree in Electrical Engineering or Computer Science

• 10+ years of industry experience in ASIC / FPGA design verification

• Experience in the entire verification process, from test plan to block and system level simulation, using standard EDA tools (Cadence Incisive suite and/or Mentor Questa)

• Experience with UVM and related verification methodologies and tools

• Experience with Block level and System level tests writing for FPGA / ASIC designs

• Experience with code coverage methodology

• Domain expertise in standard bus protocols: PCIe, SPI, I2C, LVDS

• FPGA-based co-simulation, and emulation platforms for Design Verification

• Working knowledge of System Verilog & Object Oriented techniques

• Scripting languages such as Perl, Python, Shell

• Solid debugging and problem solving skills