ASIC Manager

Employment Type: Full-Time

Location: Beaverton, Oregon (open to relocation)

About Us

Datavault AI, along with its event-technology subsidiary Event Citadel (formerly CompuSystems), operates across a diverse portfolio of technology and service divisions.

Datavault AI Inc. delivers high-performance computing software, Web 3.0 data-management solutions, and advanced audio technologies to a broad range of industries. Its Acoustic Science division licenses spatial and multichannel HD audio technologies-including ADIO®, WiSA®, and Sumerian®-to customers in sports & entertainment, events & venues, automotive, finance, and other sectors.

Event Citadel (formerly CompuSystems), founded in 1976, is a trusted provider of end-to-end event technology solutions, offering registration, ticketing, lead retrieval, and attendee-engagement services for events of all sizes across trade, association, corporate, and government markets.

Job Description

We're a fast-moving semiconductor startup building next-generation wireless audio silicon solutions. We are looking for an experienced ASIC Engineering Manager to lead external ASIC development partnerships, drive aggressive cost targets, and manage successful chip execution from architecture through production.

This role is ideal for someone who combines strong technical depth in wireless ASICs with practical business judgment around vendor management, silicon cost optimization, and execution in a resource-constrained startup environment.

Key Responsibilities

Select, evaluate, and manage relationships with external ASIC design and manufacturing vendors

Drive ASIC program execution across architecture, RTL, verification, physical design, tapeout, and production

Own vendor performance, schedules, deliverables, quality, and cost accountability

Develop and execute strategies to achieve aggressive chip cost targets in a small-company environment

Analyze and optimize ASIC cost drivers including die size, process node selection, packaging, yield, test, NRE, and production scaling

Collaborate with internal hardware, software, RF, systems, and product teams to define silicon requirements and tradeoffs

Provide technical leadership throughout the full chip development lifecycle

Review and guide ASIC implementation methodologies, flows, and EDA tool usage

Identify technical and operational risks early and drive mitigation plans

Support bring-up, validation, and production ramp activities

Qualifications

BS, MS, or PhD in Electrical Engineering or related field

10+ years of experience in ASIC or SoC development

Proven track record delivering multiple successful chip designs to production

Strong experience with wireless chipsets and wireless communication systems

Hands-on understanding of ASIC development flows and semiconductor cost structures

Experience selecting and managing external ASIC vendors and design partners

Strong understanding of ASIC cost drivers and methods for reducing silicon and manufacturing costs

Familiarity with industry-standard chip EDA tools and implementation flows

Experience working in startup or small-company environments with aggressive execution goals

Strong project management, communication, and cross-functional leadership skills

Preferred Qualifications

Experience with low-power wireless, connectivity, or RF-integrated SoCs.

Knowledge of advanced process nodes and packaging technologies

Experience with DFT, physical design, timing closure, or silicon validation

Familiarity with foundry engagement and manufacturing operations

Prior experience leading geographically distributed vendor teams

What We Offer

Competitive salary and benefits package.

A fast-paced, high-impact work environment.

Opportunity to work closely with executive leadership.

The chance to work with cutting-edge technologies and make a significant impact.

A culture of innovation, ownership, and growth.