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Design Verification Engineer (ASIC Front End)

Company:
Alyn Patrick & Associates, Inc.
Location:
Dallas, Texas, United States
Salary:
115-125,000
Posted:
November 17, 2016
Description:

Design Verification Engineer (ASIC Front End)

Dallas-Fort Worth, TX

$115-125,000 a year

This is a fast paced role working on an ASIC front end. Primary focus will be design verification of digital ASICs.

RESPONSIBILITIES:

• Digital simulation and RTL design with SystemVerilog.

• Will be involved in Timing and functional verification, Documentation, Testbench development, Scripting.

• Verification using UVM (if you have UVM or OVM please apply).

• Will interface panel design team.

• Ideal candidate will have keen eye for detail.

• Will have Scripting experience in Perl or Python and ability to test.

REQUIRED EDUCATION:

• Bachelor's BSEE

SKILLS REQUIRED:

• 4+ years ASIC design verification.

• FPGA verification and UVM methodology are strong pluses. Can read RTL/Verilog/Systemverilog.

• Digital Background, some Mixed Signal OK

Helpful terms (not necessarily used in job but indicative of skills needed): Memory design, VHDL, SystemVerilog, Digital IC, Video and Audio Processing, Microprocessor design, cadence, Physical Design, chipset, timing, virtual reality, CUDA, GPU, SoC.

JOB TYPE: Full-time

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, national origin, disability, age or veteran status.