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RTL to GDS II, Verilog, System Verilog, TCL, Perl, C resume in Austin, TX - August 2016
NIKHILA MIRIYALA
C: 816-***-**** acwd7q@r.postjobfree.com
Summary
Seeking entry-level positon/co-op in ASIC/SoC design. Design and Verification experience with Digital IC’s Professional Experience
PG Diploma in Physical design and SoC Integration, Shastra Microsystems Jan’16 – Jun’16...
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