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VLSI, FPGA, Digital Design, Verilog, C, PERL, UVM resume in Hyderabad, Telangana, 500007, India - July 2014

Niranjan Reddy

Mobile: +919********* Email : ace5na@r.postjobfree.com

Summary:

Over 18 months of experience in FPGA Validation.

Good at RTL design, simulation and synthesis using EDA tools.

Worked on multimillion gate SOC validation.

Experience in running pre-synthesis(RTL),...


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