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Project Manager

Rochester Hills, MI map
... Designed and coded of 1G and 10G Ethernet models which interact with the logic using Verilog. Developing the verification environment using DENALI PCI Express Models. 3) STORAGE ADAPTER (IBM, Rochester, MN) 06/2002 to 05/2005 Project Description ... - Jul 31

Engineer Design

Central Point, OR map
... John Bantner ** ****** ***** **** Jacksonville, OR 97530 Cell - (541) ***-**** Tools Hardware description languages: VHDL, Verilog, Abel, CPL, Warp, and Palasm Schematic entry programs: Orcad, Viewlogic, Dx_Designer, and ... - Jul 31

Project Training

India, New Delhi, Delhi map
... institute of Technology, Ghaziabad UPTU First 71 12th 2008-2010 Dashmesh Public School, Delhi CBSE First 73.2 10th 2008 S.V.M Bettiah, W.pancharan,Bihar CBSE First 78.4 Software Skills: Languages: Verilog O.S.: MS-Windows 7, MS-Windows 8 Core ... - Jul 31

Sales Engineer

Newton, MA map
... feedback control units with standard cells in the 320Mhz disk read channel using 3.0V 0.35 micron technology Generated Verilog HDL and synthesis methodologies for high-speed logic circuit synthesis Designed test benches for functional testing and ... - Jul 30

Verilog, perl, C++, VHDL, Tcl, SystemC, SystemVerilog, C, C#

United States map
... Languages: Verilog, perl, C++, VHDL, Tcl, SystemC, SystemVerilog, C, C#. PROJECTS ATPG And Fault Simulator Design [C++] Programmed in C to implement ATPG and fault simulator for combinational circuits. Implemented the ATPG in D-algorithm and PODEM, ... - Jul 30

Management Manager

Pakistan, Islamabad, Islamabad Capital Territory map
... Shalimar College Baghbanpura Lahore 2006 886 A+/1100 Computer Graphics Designing Course Peak Solutions Lahore 2004 Distinction Matriculation Shamim Higher Secondary School 2004 655/850 Workshop on FPGA/Verilog held in UET, Lahore organized by IET ... - Jul 30

verilog programming, embedd c, cadence.

India map
... Worked On Verilog Coding Projects : 1.Implementation of high speed flagged binary adder for floating point unit application. 2.High speed and area efficient booth recorded Wallace tree multiplier for fast arithmetic circuit. 3.Area-Delay efficient ... - Jul 30

Engineer Network

Philippines, National Capital Region map
... Laurel Highway, Tanauan City, Batangas Summary of Skills Adept in Adobe Photoshop and Lightroom Knowledgeable with Verilog HDL and C++ Familiar with Windows and Linux Knowledgeable with Internetworking, Routing & Switching, VLAN, LAN/WAN, Frame ... - Jul 29

Graduate Student

Sunnyvale, CA map
... of Technology (Electronics and Communication) GPA: 81.13/100 June 2011 TECHNICAL SKILLS HDL and Programming Languages : Verilog, System C, C, C++, VHDL Tools and Packages : ModelSim, Cadence Virtuoso, Xilinx 14.7, NCsim, dccompiler, PrimeTime, ... - Jul 29

Engineer Design

Parker, CO map
... Strength in large scale FPGA design and verification using VHDL, Verilog and C/C++. Experience using SystemC for network hardware architecture modeling. Education MSEE, Microelectronics/Optics, University of Texas at Dallas, December 1994. BSEE, ... - Jul 29
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