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Design Engineer Project

India map
... TECHNICAL SKILLS: Language known :Verilog, VHDL, C. Tools :ModelSim-Altera 6.3, Xilinx ISE 9.2i. ACHIEVEMENTS AND ACTIVITIES Participated in vlsi and embedded system workshop for two days. PERSONAL PROFILE: Date of Birth : 05-08-1988 Father’s name : ... - Feb 01

Engineer Engineering

India map
... Hardware programming Languages : Verilog, MATLAB 6 ACHIEVEMENTS: Published a paper titled DESIGN OF HIGH SPEED LOW POWER REVERSIBLE VEDIC MULTIPLIER & REVERSIBLE DIVIDER in International Journal of Engineering Research and Applications. Certified in ... - Jan 31

Assistant Engineering

San Francisco, CA map
... university contests and awarded the “Top 10 Associations of Beihang University” in 2011 SKILLS Languages: Java (main), C/C++, JSP, JavaScript, SQL, HTML, MATLAB, VHDL, Verilog, Assembly Sports: National Second-Class Athletes of China (Table Tennis) - Jan 31

vlsi, electronics,communication

India, Pune, Maharashtra map
... ROLE: Developer TEAM SIZE: 4 TECHNICAL SKILLS Language Skills: C, VERILOG,VHDL Software Skills: XILINX,CADENCE(Virtuoso),TANNER TOOL Areas of Interest : Communication system, Signals System,Digtal Electronics, Electronics devices And Circuits. ... - Jan 31

Project Part Time

India, Ambavaram, Andhra Pradesh map
... SSC Vikas Board of 2005-06 76% Residential secondary School, Gurazala education Academic Project: Title : Design and implementation of different multipliers Software used : Vhdl,Verilog, xilinx Role : Team member Domain : Image processing ... - Jan 31

Project Training

India, Mumbai, Maharashtra map
... Verilog (front end) . Designing of Digital & Analog IC . Low Power VLSI Design TECHNICAL SKILLS . Operating Systems : Windows XP/7 . Programming Languages : Verilog HDL, C/C++, MATLAB . EDA Tools : ModelSim 6.4a, Xilinx ISE, Mentor Graphics IC ... - Jan 31

Design Pvt Ltd

India, Bengaluru, Karnataka map
... Disciplined, versatile and big picture thinker TECHNICAL PROFICIENCY Languages : verilog and C Operating System : LINUX, WINDOWS Tools Used : Synopsys Design Compiler, Synopsys PrimeTime, SpyGlass, Xilinx Job Functions : Timing Analysis, SpyGlass ... - Jan 31

Design Engineering

India, Bengaluru, Karnataka map
... Skills: Summary of Qualifications 1) Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog. 2) Good understanding of the ASIC and FPGA design flow. 3) Very good knowledge in verification methodologies. 4) Experience in ... - Jan 30

Design Engineering

India, Bengaluru, Karnataka map
... Title: Router 1x3 – RTL design and Verification Team size :2 HDL : Verilog HVL : SystemVerilog EDA Tools : Questa -- Verification Platform and ISE Description: The router accepts data packets on a single 8-bit port called data and routes the packets ... - Jan 30

Engineering Design

India, Telangana map
... Short term course on digital Basics on digital design using design using HDL at CDAC hdl and Verilog coding HYDERABAD methodologies and test bench techniques, and some applications with FPGA kit. RESEARCH INTERESTS > Robotics > Wireless ... - Jan 30
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