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Technical Power

India, Chennai, Tamil Nadu
... ULTRA-LOW POWER SRAM DESIGN USING 9nm TFET: Design of a ultra-low power 8T Tunnel FET SRAM cell and Verilog-A model is used as instances in cadence virtuoso.To realized different SRAM designs of 6T Inwards, 6T Outwards and 8T.The proposed 8T SRAM ... - Jun 27

Sales Engineer

Hong Kong, Hong Kong, Hong Kong Island
... feedback control units with standard cells in the 320Mhz disk read channel using 3.0V 0.35 micron technology Generated Verilog HDL and synthesis methodologies for high-speed logic circuit synthesis Designed test benches for functional testing and ... - Jun 27

VLSI, VHDL, LABVIEW

India, Gandhinagar, Gujarat
... Programming Languages: C, C++, Java, Embedded C, Assembly Language, VHDL, Verilog, DBMS Software knowledge: MAT LAB, Computer Simulation Technology, ORCAD, Mentor Graphics, XILINX, LabVIEW (Core I and Core II), Altera, Cadence (beginner) SUBJECT ... - Jun 27

Design Engineering

India, Mumbai, Maharashtra
... School, Bareilly 82% 2009 10th SSC Delhi Public School, Bareilly 78% 2007 Skills Programming Shell Scripting, Perl, TCL, Verilog HDL Software Spice based simulators- Ams (ELDO) / Custom-Sim, Star-RC, Virtuoso, Calibre, Assura, Quartus II (ALTERA), ... - Jun 27

Engineer Electrical

India, Tamil Nadu
... 04175 ADDITIONAL SKILLS Assembly, C/C++, MATLAB, Verilog, VHDL, Modelsim/Questa, Quartus, Eclipse, IAR, Visual Studio, DxDesigner,, SPICE, Office, Unix . JOB TAITAIL ; POWER GENERATER I hereby declare that the above information is true regarding to ... - Jun 26

State University Design

Fairborn, OH
... TECHNICAL SKILLS Hardware Description Languages: Verilog, VHDL,RTL coding(VHDL & Verilog) Programming languages: C(Basic),C++, HTML, Python Simulator Tools: Xilinx ISE,RTL Compiler, Cadence Virtuoso, Synopsys Tetra Max, Multisim, ModelSim, Saber, ... - Jun 26

Software Engineer Manager

India
... Technical Expertise: Languages : C, C++, Win 32, VC++, Embedded C++, ATL/COM, VB 6.0, C#, ADO.NET, HTML, XML TCP/IP, Verilog, .NET 3.5/4.0 Platform/Operating System : RHEL 5.0, Windows 7, Windows 8, Windows 2003, 2008, 2012 Server, Win CE 5.0 ... - Jun 26

Project Sap

India, Hyderabad, Telangana
... Project: Design and implementation of hash algorithm using Verilog hdl Objective: the purpose of this project is to implement cryptographic hash functions message digest 5 (MD5) algorithm and secure hash algorithm on Xilinx, by developing the code ... - Jun 26

Software Electrical Engineering

San Clemente, CA
... Skills: Bash scripting, IBM Product Suite, RHEL Advanced troubleshooting and debugging of computer hardware and software Soldering, Circuit Design (Pspice, Mentor Graphics) Knowledge of Java, C, Verilog, Matlab - Jun 24

Computer Engineering Software

San Jose, CA
... Algorithm Design, Software Engineering, Computer Networks, Operating Systems Design, Circuit Analysis, Technical Skills:C++, Verilog, Selenium, Java, HTML, CSS, Linux, XML, MacOSX, Windows, Batch Scripting, AutoCAD, Solid Works, Microsoft Excel, ... - Jun 24
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