verilog resumes 5
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Project Electrical

... S.S.L.C from Bharatha Matha Vidya Mandira, Bangalore in 2004, with 74.72% TECHNICAL SKILLS Languages : C, C++, VHDL, Verilog and 8051 Assembly level language Operating System : Windows XP, Windows 7, Windows 8 Packages : Gnu, Eclipse, Xilinx, Keil, ... - Nov 07

Design Engineering

India, Bengaluru, KA
... – 400 080 Summary of Qualifications • Good understanding of the ASIC and FPGA design flow • Experience in writing RTL models in Verilog HDL and Test benches in System Verilog • Very good knowledge in verification methodologies • Experience in using ... - Nov 07

Design Project

India, Bengaluru, KA
... • D igital System Design using Verilog. • RTL Design and Verification. • About Synthesis,Simulation and Test bench. • A bout FSM and Memory. • About Tasks and Functions. • In t roduction to ASIC Design Flow. • A bout FPGA Architecture. • Hands on ... - Nov 06

Design Computer Science

India, Bengaluru, KA
... Published paper on “Implementation of USB 3.0 SuperSpeed Physical Layer using Verilog HDL” at International Journal of Computer Applications (IJCA) 95(24):1-5, June 2014. Published by Foundation of Computer Science, New York, USA. Projects 1. Design ... - Nov 06

Customer Service Design

Tallmadge, OH
... Development Environments and Tools: CVS (Concurrent Versions Systems) Matlab: project on the treatment of signals HDL: VHDL, Verilog (ASIC, FPGA, CPLDs ), ISE, Vivaldo RTL Simulator: Cadence Affirma NC Verilog Simulator v3.0 (s12), ModelSim tb.Code ... - Nov 06

Engineer Design

Denver, CO
... ( Proficient in high level sequential (C, Assembly, Pascal) and concurrent HDL (VHDL, Verilog) programming techniques. ( Bachelor's and Master's Degrees in Electrical Engineering, over 10 years post -graduate experience. ( Excellent analytical ... - Nov 06

Design Engineering

India, Bengaluru, KA
... HDL: Verilog HVL: SystemVerilog EDA Tools: Modelsim, Questa -- Verification Platform and ISE Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel-0, ... - Nov 06

Automation Software ''Logi.Doc'', I&C Software Prodok and Conval.

India, New Delhi, DL
... T, Gmbh, Germany) Software / Hardware Languages : Graphical language (IEC 61131-3) functional block diagram, ladder diagram, C, VERILOG (Hardware Descriptive language) Operating Systems: Windows (XP, Vista,7& 8.1) & Linux (Ubuntu 10.4 & 11.04) VLSI ... - Nov 06

Electrical Engineer Service

Chicago, IL
... Hardware language such as Verilog with tools like Modelsim, Quartus II (6.0), other language like Tcl/Tk, other skills like DSP . Simulation tools such as Hspice,Pspice,LTspice,Matlab,SimpleScalar,Cacti(6.5),Wattch, SimpleScalar, Cacti(6.5),LabVIEW ... - Nov 05

Software Engineer Java

San Jose, CA
... Designed a convolutional encoder by using Verilog language 07/2011 . Created a PXA270 embedded software environment in Linux 04/2011 (Used Qt language to make a game on the PXA270 processor) . Effectively used JAVA to make a matrix calculator 03 ... - Nov 05

Office Electrical Engineering

India, New Delhi, DL
... LANGUAGE : C, C++, Verilog HDL, Matlab . . OPERATING SYSTEM : Windows, DOS, Microsoft Office. EXTRA CURRICULAR ACTIVITIES AND AWARDS . Participated in High Altitude Trekking Program covering 110KM and gained 10565 feet height. . Participated in ... - Nov 05

I am an Electrical Engineering student. I am proficient in cadance.

United States
... Schematic, CADENCE Encounter Tools, Synopsys TetraMax, Xilinx ISE Tool, and MATLAB Hardware/ Programming Languages: VHSIC HDL, Verilog, System Verilog, C/C++, SQL and Perl WORK EXPERIENCE Assistant System Engineer-Trainee Aug 2012 to July 2013 TATA ... - Nov 03

Design Engineer Assistant

Chicago, IL
... TECHNICAL SKILLS Programming Languages: C, C++, Visual Basic, HTML Scripting Languages: TCL/TK Hardware Languages: VHDL, Verilog HDL Tools: MS Office, Xilinx, MATLAB, P-spice, Keil, UNIX, Cadence Virtuoso ACTIVITIES AND ACHIEVEMENTS AFFILIATIONS: ... - Nov 03

vlsi design

India, Bengaluru, KA
... Technical Skills Programing 8086 Assembly Language, ARM, C Languages Known : Language, Verilog HDL. Tools Used : Xilinx, Cadence, Coventerware (MEMS tool), Miktex, MAT LAB. OS Worked On : Windows XP/ Vista/ Windows7/Windows 8. Verilog AREA OF ... - Nov 03

Assistant Design

India, Mumbai, MH
... • Created a front end VLSI design of a 5 stage pipelined processor using Verilog HDL Xilinx ISE tool. Designed the processor based on MIPS architecture with 3 bit instruction set over 50 instructions. Designed the processor to have 8 Byte Memory, 8 ... - Nov 03

High School Project

... Bureau Levels: A1/2: Basic user - B1/2: Independent user - C1/2 Proficient user Programming: Java, C++, C#, C, SQL, HTML, Verilog Computer skills Information Technology: Networking( TCP/ IP, UDP) Development Environments: Eclipse, Microsoft Visual ... - Nov 03

Design Project

India, Vellore, TN
... Of Secondary 2005-06 71.60 Golconda Education TOOLS AND LANGUAGES Scripting language : PERL Hardware description language : Verilog-HDL (IEEE Standard 1364-2001) Pre-layout simulator : NC-launch (Cadence), ModelSim (Mentor Graphic) Synthesis tool : ... - Nov 03

Project High School

... Diploma:Verilog Hardware Description Language In this project, a CPLD IC was burned using CPLD trainer kit with the help of Verilog HDL language. Technical Skills: General purpose languages : C& C++ Assembly Languages : PIC programing,8051, 8086,ARM ... - Nov 03

Engineering Engineer

India, Ahmedabad, GJ
... Used Synopsys tool chain to perform this project from RTL to GDS-II form Design and synthesize the cache controller Designed cache controller Verilog RTL for 1KB fully associative write back buffer cache. Used Synopsys tool chain for simulation, ... - Nov 03

Computer Science Project

Buffalo, NY
... Data Integration Modern Networking Concepts Computer Architecture Multimedia Systems Algorithm Analysis and Design Machine Learning Software Engineering TECHNICAL SKILLS Java, C++, C#, MySQL, Verilog, MATLAB, HTML, C, Ubuntu, Windows, Macintosh. ... - Nov 02
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