Verilog Resumes

Sign in
Search for: Jobs   Resumes

Show Map Get new resumes like this by email Resumes 1 - 10 of 3907

Design Project

India, Bengaluru, Karnataka map
... Good knowledge of Verilog RTL coding. Basic knowledge of ASIC flow. Basic knowledge of UART protocol. Good understanding of Object-oriented programming (OOP) concepts. Skilled in HVLs such as SystemVerilog. Good debugging skills. Good understanding ... - May 27

Computer Engineering

Odessa, FL map
... TECHNICAL SOFTWARE PROFICIENCY Experienced in Microsoft Office Suite, C, C++, Java, Verilog, VHDL, Cadence Virtuoso, HSPICE, Xilinx ISE, Windows and Linux development environments. WORK EXPERIENCE Student Assistant, 2014 - Present University of ... - May 26

Electrical Engineering Design

San Diego, CA map
... and Systems Linear Electronic Fundamentals Object Oriented Programming and Design in C/C++/Java Advance Digital Design in Verilog(VHDL) Machine Organization and Assembly Language (MIPS) Skills Languages: C, C++, Java, Assembly Language (MIPS), ... - May 26

Design Electrical Engineer

United States map
... Scripting tools: C++,Perl, VHDL, VERILOG, System Verilog. Simulation Tools: CADENCE, TETRAMAX, Synopsys (Waveview, Design Vision, Nano Time), Mentor Graphics Modelsim, Assura, MATLAB. Platforms: UNIX, Windows. Areas of Interest : ASIC Design, ... - May 26

Engineer Design

Dallas, TX map
... A group of communication students developed a Verilog program for Gaussian noisy channel. We designed the chip with Cadence Digital Logic Design Flow tools. The chip emulates a Gaussian noisy channel - any signal at the input appears Gaussian noise ... - May 26

Electrical Engineer Design

Cupertino, CA map
... Languages: VHDL, Verilog, System Verilog, RTL and TTL Scripting, Perl, Shell, • C/C++, Embedded C, Object Oriented Programming, UNIX (Makefile), Tools: Xilinx ISE, Cadence Virtuoso, Modelsim, OrCAD, PSpice, VCS, MATLAB, HSPICE, and • Synopsys TCAD. ... - May 26

Engineer Design

United States map
... EDUCATION MS in Electrical Engineering - San Jose State University, San Jose, CA August 2015 BE in Electronics and Communication – Visvesvaraya Technological University, Belgaum, India May 2012 SKILLS Languages: C, System Verilog, Verilog, PERL, Net ... - May 26

Manager Project

United States map
... admitting officer and evaluated staffing assignments of Hospital using concepts of Queuing theory Implementation of GMSK on FPGA Fall 2012 Utilized Verilog in implementing GMSK on Xilinx SPARTAN-III kit for demonstrating GMSK for educational purpose - May 26

vlsi design and verification engineer

India, Mumbai, Maharashtra map
... course from Maven Silicon VLSI Design and Training Center, Bangalore (January 2015 – June 2015) VLSI Domain Skills: HDL: Verilog HVL: SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB ... - May 26

Engineering Project

India map
... Application Software : MATLAB, Verilog HDL . Packages : MS Office, Photoshop SKILLS / STRENGTHS: . Positive and Realistic Attitude. . Good Communication skills. . Plenty of experience working in teams (presentations, sports) has helped me develop ... - May 26
1 2 3 4 5 6 7 Next