India, Chennai, TN
... Lock System Core Technology : VLSI Environment : Verilog
in Xilinx Role : Design, Coding, Manual Testing, Functional Testing, Documentation Team Size : 3 Nowadays many of the electronic lock system became unsafe due to the hacking of passwords. ...
- Mar 29
... cell manual and automatic place and route Software: Cadence: Virtuoso, Analog Design Environment (ADE), UltraSim, Encounter, NC-Verilog
, SimVision, Wavescan, Assura Synopsys: Design Compiler, CosmosScope, Prime Time Mentor Graphics: GDT, AutoLogic, ...
- Mar 27
... Python, PeopleCode, SQR, SQL, Verilog
, VHDL, PSPICE, Matlab, C, C++, JAVA, COBOL Hardware Platforms: Intelx86, ATMEL AT89C51, Motorola68332 Packages: MS Office, STAT Database: Oracle, MS Access, MS SQL Web Technologies: HTML, XML, JAVA EDUCATION: 1. ...
- Mar 27
... Ten years of collaboration on VHDL and Verilog
ranging from RTL though Gate Level including synthesis, timing, constraint definition and checking as well as place and route. Throughout this process, I advised synthesis developers, helped create more ...
- Mar 27
... Database Management System, Electronics, Graphical User Interface, Graphics Software, Labview, Lighting, MATLAB, Microsoft Visual C, Multimeter, OpenVMS, Operating Systems, Oracle, Oscilloscope, Project Management, Real Time, Verilog
, Visual Basic. ...
- Mar 26
Los Angeles, CA
... • Community Service through Kellogg Honors College Fall 2007-June 2011 o Help set up events, organize and give people directions • Hands-On Experience in Labs o Programming using C, C++, MATLAB, Verilog
, and Assembly o Using a voltmeter, ohmmeter, ...
- Mar 26
... SKILLS PROFILE - Strong SOC and partial IP Verification Experience i nvolving use of latest HVL’s ( SystemVerilog, System Verilog
HDL, C, VHDL etc) with different Methodologies like SVBCL (Similar to VMM/OVM) and URM - Majorly ...
- Mar 25
Thousand Oaks, CA
... SKILLS LANGUAGES: Verilog
, VHDL, C/C++, Assembly TOOL: Quartus II, ModelSim, Synopsys, Altera Maxplus II, Xilinx FPGA Express, Verilog
, Concept, PADS Logic, PADS Layout, Allegro, Pspice. PLATFORMS: IBM PC's, Sun Workstations ...
- Mar 23
... control the process ENG I N EE R I NG SOFT SK I L LS Software S kills : M ini tab16, Matlab2012b, SPSS, AutoCAD, ModelSim, V HDL &Verilog
, Lab view Report Writers : M S Project, MS Visio Operating systems : W indows /Macintosh/ Linux E D UCAT ION U ...
- Mar 22
Canada, Toronto, ON
... Led development of two verification commercial verification tools: - RuleBase static verification and FoCs for Dynamic verification of VHDL & Verilog
. Leading of the above two verification tools in parallel included: time to market solution, ...
- Mar 22
... Hardware programming: Verilog
, System C, VHDL Internship Experience ASIC Design Engineer in Chip and System Research Centre in Shanghai Jiao Tong University March 2010 to July 2011 Worked in team in a commercial ASIC design project. Coded the block ...
- Mar 20
San Jose, CA
... Probability and Statistics Digital Signal Processing Applications of Digital Signal Processing ASIC design using Verilog
hardware description language EXPERIENCE CompTechS Cupertino, CA 9/2007 to 2/2008 • Hardware & Software Installation • ...
- Mar 19
... Worked with C++,SQL Server 2005, VERILOG
, PSPICE, Python, Unix and assembly language • programming for microprocessors as part of coursework.. Comfortable with CORELDRAW to draw designs for power point presentations. • Familiar with SolidEdge ...
- Mar 18
... Loading data in a coalesced fashion and using Double-buffering to load input file 11-tap 16-bit Folded Pipelined LP-FIR filter (Verilog
) Spring 2012 . The filter used only one Booth recoded Wallace Tree multiplier with 2 stage pipelining by folding ...
- Mar 16
India, Mumbai, MH
... > Hardware Language: - VHDL & Verilog
. > Network Communication (CCNA). EXTRA CURRICULAR ACTIVITIES:- . Seminar on "Space Vector Pulse Width Modulation". . Undergone "personality Development Workshop", organized by college. . Vocational training in ...
- Mar 16
India, banglore, KA
... ASIC/VLSI Physical Design/Layouts/Verilog
/Verification domain in an organization of repute in the industry to be part of the growth and development of the organization and to enhance my knowledge on par with industry expectations and requirements. ...
- Mar 14
India, Yamunanagar, HR
... Hardware Description Languages : VHDL, Verilog
. Assembly Languages : 8051 (Microcontroller), 8086 (Microprocessor). Design Tools : OrCAD, MATLAB, Xilinx ISE 8.2i and ModelSim. Soft Computing Algorithms : BBO, Genetic Algorithm, BB–BC and Firefly ...
- Mar 14
San Diego, CA
Language . Synopsis DC compiler . Synopsis Prime Time . Synplify . 0-In ABV . Cadence NC Simulator . Mentor ModelSim Simulator . C++, Unix, Perl, TCL . IBM Power PC, ARM9 CPU . Mentor Boardstation schematic capture . Cadence Concept ...
- Mar 11
United Arab Emirates, Dubai, DU
Silos (VLSI Circuit Design) Major subjects . Digital Signal Processing . Advanced Telecommunication . Signals & Systems . Networking Area of Expertise . Project Management/Implementation. . Inter-functional co-ordination . Field Operations ...
- Mar 10
Canada, Airdrie, AB
... < Created custom memory models and test benches (Verilog
). < Circuit simulation, characterization, schematic entry, and layout work (Hspice, Spectre, Cadence). CAD Tool Designer < Supported PCB CAD design environment through the creation of cost ...
- Mar 06