verilog resumes 4
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Engineering Power

Hayward, CA
... GPA: 8.0/10.0 TECHNICAL SKILLS Hardware skills: VHDL, Verilog, System Verilog, OVM, UVM, Cadence, Synopsys, LabView, Licensed HAM radio operator Software skills: C, C ++, MATLAB, UNIX, Perl, TCL, Shell, OOP programming COURSEWORK VLSI Circuits and ... - Sep 10

Project High School

India, Hyderabad, Telangana
... JUNIOUR COLLEGE 2005-2007 81.9 SSC GAYATRI ENGLISH MEDIUM 2004-2005 70.33 HIGH SCHOOL Technical Skills: Operating Windows : MS Office (Word, Excel and PowerPoint) Programming Languages : Verilog Tools : VCS, HSIPCE, Microwind Certifications: . ... - Sep 10

Engineer Engineering

India, Hyderabad, Telangana
... TECHNICAL SKILLS Languages : Verilog,Basic concepts in PERL Simulator Tools : VCS simulator, H-Spice Synthesis Tools : Design compiler, IC Compiler Operating Systems : Windows, LINUX AREAS OF INTEREST Digital electron. ACADEMIC PROJECTS: M.TECH: ... - Sep 10

Project High School

India, Hyderabad, Telangana
... > Languages : Verilog,Basic of PERL,C, System Verilog basic > Simulator Tools : Synopsys VCS simulator > Synthesis Tools : Synopsys DC compiler > ATPG Tools : Synopsys Tetramax > Operating Systems : Windows, LINUX Project: Design and Verification of ... - Sep 10

Engineer Project

India
... Have hands on experience on System Verilog Verification and worked on developing verification environment using SV. Possess good knowledge on UART protocol. Have good knowledge and work experience on Altera-FPGA. Knowledge on Linux. Good ... - Sep 10

Engineer System

Vacaville, CA
... Jan/2006 - Apil/2006 (FPGA Class) Advance Verilog 2001 syntax, Algorithm State Machine (ASM) design of FIFO, PCI, UART, and Microprocessor. RTL coding, State Machine, set up time, and register. Project using Altera Quartus II, SW with simulated with ... - Sep 10

VLSI ENGINEER

India, Bengaluru, KA
... 2007 67 Project Title : INTER-INTEGERATED CIRCUIT BUS Platform : RTL Coding (Verilog /System Verilog/VHDL) Duration : 1 Month Description : The I2C bus is a popular serial bus, two wire interface use in many system because of its low overhead. The ... - Sep 09

Representative Design

India, Kolkata, WB
... Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL. Strong understanding of Digital electronics and solid state devices. knowledge of Static Timing Analysis and Good ... - Sep 09

Verilog, VHDL, C, Physical Design, RTL synthesis/Coding

India, Vijayawada, AP
... Proficient: Experience in writing RTL Codes, FSM Based Design in Verilog HDL and Test benches in System Verilog. Good Understanding of the ASIC and FPGA Design flow and Digital Design. Worked on the Digital as well as analog and high speed VLSI ... - Sep 09

Project Engineer

India, Hyderabad, Telangana
... Languages: Fluent in C, basic knowledge in VHDL and VERILOG Packages: Familiar with Microsoft PowerPoint and Word. EXTRA CURRICULAR ACTIVITIES > Actively participated as coordinator in a work shop at college level conducted on latest advances in ece ... - Sep 09

Electrical Engineering Control

Rochester, MI
... of related theory and gained MATLAB programming skills Embedded System Design: Skin Detection based on NIOS 2 Processor Using Verilog December 2013 > Built a NIOS 2 processor with Altera on the DE2-115 FPGA board > Developed a complete algorithm to ... - Sep 08

VHDL, Verilog, Embedded, Assembly Language C, C++, Java

India
... Analog and Digital Electronics Computer Hardware and Networking Communication Theory Technical Skills: Languages : VHDL, Verilog, Assembly Language, C and C++ Package : MS-Office Operating System : Windows Certificates Obtained: Advanced Diploma in ... - Sep 08

Engineering Electrical

Thornhill, VA
... thinker and also extremely practical from multiple large group projects • Competent programmer in Java, VBA, VHDL, Verilog, MATLAB, Maple, Perl, Python, C# and C++ • Experience working with electrical laboratory equipment through exposure to ... - Sep 07

Software Engineer Computer Science

Canada, Toronto, ON
... ADHISH ROY Scarborough, ON M*K *S* Phone: 647-***-**** Email: acfteb@r.postjobfree.com Software Skills: Languages: Java, C/C++, SQL, MIPS, Eiffel, Verilog. Web: HTML, CSS, JavaScript. Programming Tools: Eclipse JDT, jEdit, Eiffel, Rodin, Oracle. ... - Sep 07

Project Intern (IC Team) Saankhya Labs Pvt Ltd.

India, Bengaluru, KA
... PUBLICATIONS Design and Implementation of Neighborhood Processing a) Operations on FPGA using Verilog HDL. Publisher: IOSR journal of VLSI and Signal Processing (IOSRJVSP), [Volume 4, Issue 1]. Design and Implementation of a Digital Image Processor ... - Sep 07

High School Quality

India, Bengaluru, KA
... HDL’s : Verilog and VHDL. HVL’s : Basic Knowledge on System Verilog. EDA Tools : Xilinx ISE Design suite, Mentor Graphics. Software Languages : Basics of C. Operating Systems : Windows, Basics of Linux. Bachelor of Technology in E.C.E with 61.8 2009 ... - Sep 07

Design Engineering

India, Bengaluru, KA
... Technical Skills: • System Verilog • System Verilog Assertion • Assertion Based Verification • Verilog HDL • VHDL • Hardware Designing Software’s: Cadence RC Design Compiler, Virtuoso, ncSim, SoC Encounter, Assura, Layout/LayoutXL, Xilinx, Altera ... - Sep 07

Front end Design & verification

India, Bengaluru, KA
... Experience: Ph:916******* TEN months Industrial training in Company Perfect VIP's E-mail:Vamsikumar solutions Pvt.Ltd, Bangalore under the Silicatech acfsqv@r.postjobfree.com Institute on a live project in system verilog UVM,VMM Verification. ... - Sep 06

Engineering Training

India, Coimbatore, TN
... Higher Matric Board 2005 77.45 X Sec.School, Coimbatore TECHNICAL SKILLS • PROGRAMMING LANGUAGES: C, C++,HTML,JAVA • HARDWARE LANGUAGES:VHDL,VERILOG • ELECTRONICS CADD AREA OF INTEREST • EMBEDDED SYSTEMS • DIGITAL SYSTEM DESIGN • NETWORKS & DESIGN ... - Sep 06

mtech vlsi student

India
... Languages Programming: - Verilog, Microcontroller, C Language, C++, Perl Scripting. ACADEMIC PROJECT Automatic Railway Gate control The project is designed using 8051 Microcontroller. One group of transmitters and receivers is fixed at upside and ... - Sep 06
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