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Project Engineering

India map
... Technical Skills • Languages: Matlab, vhdl, verilog, lab view, simulink, hspice, eldo, sprocess, sdevice, verification. • Operating Systems: Windows • Packages Known: MS Office (Word, PowerPoint, Excel) Personal Details Date of Birth: 11th November ... - Mar 02

Project High School

India map
... LANGUAGES: C, VERILOG and VHDL. CONCEPTS: GSM, Transmission, PDH & SDH. PROJECT: Mini Project: Automated vehicle for physically and visually handicapped. Major Project: VHDL implementation of DIGITAL GPS RECEIVER. Description: In this project a ... - Mar 02

vlsi design and verification engineer

India map
... Board : 2007 Year :85.8 Percentage Secondary : Board of Secondary School Education, Andhra Pradesh Board : 2005 Year : 87 Percentage Technical Skills: Programming Languages : C, C++ HDLs : Verilog, VHDL HVDLs : System Verilog, OVM,UVM Scripting ... - Mar 02

CPU, ASIC, SoC, FPGA Design and Embedded Systems

Rochester, NY map
... Bachelors in Electronics and Communication Engineering (June 2013) Anna University, India GPA: 7.0/10 » Skills Languages C, Verilog, System-Verilog, Perl, Matlab, Bash, C++, Open-MPI RTOS UNIX, QNX (TCB, IPC, POSIX threads, modeling and UML) ... - Mar 01

Engineering Project

India, Mumbai, Maharashtra map
... Description : VHDL/VERILOG : Six Weeks (17th June 2013-26th July 2013) Duration ACHIEVEMENTS : • Organized free computer awareness programs at different government school. • Successfully executed and managed the Annual Sports Day. • Volunteered ... - Mar 01

Assistant Engineering

India map
... Department of ECE Faculty Development 18th to 20th June Program on VLSI 2012 Design using Lovely Professional ( 3 Days ) Verilog University Department of ECE Participated in Faculty Development Program on Virtual Labs Organized by ECE Department at ... - Mar 01

Verilog,Vhdl,Embedded C,Assembly,Vlsi,Embedded,C,Fpga,Psoc,Cmos,Digit

India, Gujarat map
... KNOWLEDGE PREVIEW C,VHDL,VERILOG, ASEMBLEY and EMBEDDED C– Languages XILINX ISE DESIGN SUITE,KEIL,CADENCE,ORCADE LAYOUT PLUSE,PSPICE SIMULATION and MODELSIM – Tools used RTL designing & verification and digital design logic – Good understanding PSOC ... - Mar 01

Design Engineering

San Jose, CA map
... Bachelor of Engineering, Electronics and Communication Engineering, May 2013 Relevant Coursework: Microprocessors & Microcontrollers, Verilog HDL, Analog Electronic Circuits, Digital Signal Processing. TECHNICAL SKILLS Hardware Description Languages ... - Mar 01

Project System

India, Gurgaon, Haryana map
... Proficient in design using Verilog HDL, VHDL, System Verilog. Proficient in verification using System Verilog UVM. Protocols UART, I2C, SPI. Tools used ModelSim, Questa Sim, Xilinx ISE, Altera Quartus & Active HDL, PSPICE. PROFESSIONAL EXPERIENCE ... - Mar 01

asic/fpga

India, New Delhi, Delhi map
... Experience Fresher Key Skills C, Embedded Systems Operating System Digital Electronics Analog Electronics Intel-8051, Windows 98, XP, 7,8,8.1 IDE Packages: KEIL C code, VHDL,Verilog MS Office suite viz. Circuit Simulation: Pspice, LTspice, uVision ... - Mar 01
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