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Engineer Test

Santa Clara, CA map
... 9 U niversity of California Santa C ruz 1994 B.S Computer Engineering Languages: Assembly on 6800/80x86, C, C++, Python, Java, Ruby, Java, Perl, Tcl, Tk, Expect, Selenium, Verilog, HTML. Stanford University 2013 - Present Advanced P roject ... - Jan 25

Electrical Engineering Design

Lancaster, CA map
... Created a project in Xilinx ISE and implemented the state machine step by step in Verilog . Simulated and debugged the code using ModelSim to make sure it ran correctly and then downloaded it to the FPGA board . Connected the FPGA board with the ... - Jan 24

Engineering Support, Typewell

Fulton, IL map
... Verilog, Synopsys, Virsim, vcs, tcl scripting and various in-house design tools are used to accomplish this task. This was a telecommute position. Nov 98 - Aug 00: ASIC Design/Verification Engineer, Aerotek Contract Eng. Services, 2810 Crossroads ... - Jan 24

Engineer Test

Santa Clara, CA map
... 9 U niversity of California Santa C ruz 1994 B.S Computer Engineering Languages: Assembly on 6800/80x86, C, C++, Python, Java, Ruby, Java, Perl, Tcl, Tk, Expect, Selenium, Verilog, HTML. Stanford University 2013 - Present Advanced P roject ... - Jan 24

ASIC design, Verification

Sunnyvale, CA map
... / 4.00 B.S., Department of Electrical Engineering, Beijing University of Technology July 2013 Major GPA: 3.87 / 4.00 SKILLS Verilog, Perl, C/C++, system C, Cadence Virtuoso, Synopsys Design Compiler, Modelsim, TetraMax, Encounter, PrimeTime ACADEMIC ... - Jan 23

Electrical Engineering graduate (UTSA)

San Antonio, TX map
... (Word, PowerPoint, Excel) OrCad Capture (PSpice) and PCB editor Familiar with C++, Verilog & Assembly languages Degree concentration in Power Engineering • Fluent in both English and Spanish • Trained to design, analyze, debug and solder circuits • - Jan 23

Data Engineering

India, Ambavaram, Andhra Pradesh map
... Technical Skills: Programming Language: C Hardware Description Languages: VHDL, Verilog Circuit Design and Analysis Tool: Altera Quartus II, Xilinx FPGA: Acquainted with Altera DE2 Boar Academic Projects: Title : FPGA Implementation of Sine and ... - Jan 23

Engineer Test Cases

India, Bengaluru, Karnataka map
... Verification Engineer 4 months (June-2013 - September 2013)training at Maven Silicon Summary Of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing Test benches in System Verilog and methodologies like UVM, OVM. ... - Jan 23

Design Power

Philadelphia, PA map
... Embedded Systems Fundamentals of systems Analog and Mixed Mode Introduction to V HDL and Global Engineering Project VLSI Verilog Management TECHNICAL SKILLS Cadence Tools : Virtuoso, Composer Schematic, Layout Editor, SoC Encounter RTL-to-GDSII ... - Jan 22

Project System

India, Bengaluru, Karnataka map
... 2008 passout with 73.63% Other known language: • System VerilogVerilog • UVM Methodology • perl • C Skills: • Good understanding of fundamentals of Transistors and circuit theory. • Good knowledge of IC Fabrication process. • Good knowledge of ... - Jan 22
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