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Engineer Project

Santa Ana, CA
... Project Name: MIPS Processor Design Project 32 Bits Developed a Modified MIPS Processor using Xilinx ISE and coding done in Verilog language. Successfully implemented 32 bit modified MIPS. Work involved Functional Verification of blocks in IP and ... - Aug 24

ASIC Physical Design Engineer

Santa Clara, CA
... : Verilog HDL, Perl, C, System Verilog, C++ Tools : Synopsys Design Compiler, Vivado, Leonardo Spectrum, H-spice, Encounter, Prime time, Eldo, Matlab, Synopsys Formality, Mentor Graphics IC studio, Mentor Graphics Pyxis, Mentor Graphics Calibre. ... - Aug 24

System High School

... 2006 Skills Sequential Language C, C++ language, Verilog, System Verilog Operating system Windows 7,Linux(Red Hat),Windows Xp Project Work Energy saver using microcontroller 8051: Basically it was controlling switching of A.C appliances using relay. ... - Aug 23

Electrical Engineering Software

Israel, North District
... ●Fluent in VHDL, C, knowledgeable in verilog. ●Fluent in, MODELSIM, QUARTUS, NIOSII, SignalTap and all Altera tools. ●Fluent 10G ETHERNET and communication. ●Experience with implementations of finance algorithms, Low latency design. ●Experience with ... - Aug 23

Manager Sales

Arvada, CO
... -Developed training courses for the use of VHDL and Verilog in FPGA design. ASIC Design and Test Engineer 7/90-4/95 -Texas Instruments and NCR Microelectronics EDUCATION B.S. in Electrical and Computer Engineering Montana State University, Bozeman, ... - Aug 23

Engineer Sales Executive

... Programming languages: Verilog, VHDL, C. Project: Real Time Spike Sorting System for Brain Machine Interface. Project Theme: Writing a code to implement an algorithm to detect the various of spikes in neuron signal in digital form. Miniproject: MIDI ... - Aug 23

VlSI design

Dallas, TX
STATUS-OPT SAMEER RAMAKRISHNAGARI **** ****** ****** ****, *** 2009W Mobile: 405-***-**** Dallas TX 75254 PROFILE Strong RTL Coding in Verilog VHDL, System Verilog for ASIC or FPGA ... - Aug 22

Data Computer Engineering

Mobile, AL
... Early Cache Miss Determination using MNM blocks (HDL, Tools: Verilog, Xilinx ISE, Questasim) Implemented Table MNM (Mostly No Machine) and Replacement MNM techniques on 5 level cache. Achieved reduction in miss rate by 23%, execution time by 6.2% ... - Aug 21

IC Design Engineer

Austin, TX
... June 2013 Bachelor of Technology – Electronics: VES Institute of Technology [GPA: 3.86/4] SKILLS: Programming Languages: Java, JSF, JSON, C/C++, Verilog, VHDL Application Software: Cadence, MATLAB, Xilinx ISE, ModelSIM, AUTOCAD, EAGLE, SIMULINK, ... - Aug 21

RF Consultant

Saudi Arabia, Jeddah, Makkah Province
... page, Visio, Project, Access Operating systems: Microsoft Windows XP, Sun Solaris UNIX Software languages: C, Matlab, Verilog, Assembly languageetc REFERENCES: 1.Aamir Naveed, RF Project Manager, Ericsson,,+92 344 *** ** ... - Aug 21
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