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Digital electronics,verilog,system verilog,UVM.

India, Bengaluru, Karnataka map
... Mahendra K R #**,******* ******,******, Bangalore Email: acn2mk@r.postjobfree.com Karnataka, India –560064 Mobile: +91 814******* Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL ... - Jan 29

Design Engineering

India, Allahabad, Uttar Pradesh map
... Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Experience in writing RTL models in Verilog HDL and test benches in SystemVerilog > Very good knowledge in verification methodologies > Experience in using industry ... - Jan 29

Project Engineer

India, Bengaluru, Karnataka map
... • Hands on experience with Synopsys VCS RTL simulator. • Exposure to System verilog, Test Bench development, trackers, checkers, assertions, and coverpoints. • Experience with FPGA debug tools, Identify/Chipscope/ILA, CSA • Platform validation ... - Jan 28

Engineer Project

India map
... Verified the RTL module using OVM. Generated functional and code coverage for the RTL verification sign-off Description: The functionalities of different arbiter schemes are verified in this project. We have verified the Round Robin Arbiter, Fixed ... - Jan 28

Mtech Fresher

India map
... Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools. . Experience in Simulation, Synthesis, MAP and Place & Route. ACHIEVEMENTS: . Awarded second prize in paper on "video security for ambient intelligence", Vellore. . ... - Jan 27

Project Software

India, Bengaluru, Karnataka map
... Goldmine mines the simulation traces of a behavioral register transfer level (RTL) design using a decision tree based learning algorithm to produce candidate assertions. These candidate assertions are passed to a formal verification engine. Software ... - Jan 27

verilog,vhdl VLSI front end design, systemverilog and back end design

India, New Delhi, Delhi map
... About Project: It’s a general central processing unit RTL design interfaced with a memory unit which stores the command to be fetched in it. It operates some basic functionality and design of its part like ALU, control units, register array, ... - Jan 27

Project Design

India, New Delhi, Delhi map
... About Project: It’s a general central processing unit RTL design interfaced with a memory unit which stores the command to be fetched in it. It operates some basic functionality and design of its part like ALU, control units, register array, ... - Jan 27

intern in stmicroelectronics

India, Bengaluru, Karnataka map
... Technical Skills:- • Programming Languages :C • Hardware Description Languages : Verilog, VHDL, SPECMAN • Scripting Languages : Perl • EDA Tools : Synopsys – VCS : Cadence – Incisive sim, RTL compiler, Encounter, Virtuoso : Mentor Graphics - ... - Jan 26

Verilog,VHDL,System verilog,shell script,Perl script

India, Noida, Uttar Pradesh map
... Wrote algorithms in Verilog HDL at RTL for Architecture. Verified with several testbenches and synthesized in Xilinx ISE The design has been implemented on a range of FPGAs to compare the performance . Common-Gate Low-Noise Amplifier(LNA) A fully ... - Jan 26
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