rtl resumes

Design Engineering

... AJIN KUMAR Ittina Sarva Apartments II, Hongasandra,Bangalore, Email: acfydm@r.postjobfree.com India – 50068 Mobile: +91 875******* Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in ... - Sep 15

Design Electrical Engineering

Los Angeles, CA
... *** #** Los Angeles, CA90007 acfwsa@r.postjobfree.com Tel: 213-***-**** Career Objective Seeking a fulltime/intern position in ASIC design/verification Core Qualification Solid working experience with RTL design and verification using Verilog, ... - Sep 12

High School Design

India, Bengaluru, KA
... Technical Skills: HDLs: Verilog Scripting Language : Perl,TCL EDA Tool: RTL Compiler, Conformal Low Power, Cadence Encounter, Olympus Domain: ASIC/FPGA Design Flow, Digital Design methodologies Perl . > finding the cells and instances in given ... - Sep 10

Engineering Power

Hayward, CA
... RTL, Validation, and Automatic Place and Route of a Low Power FFT Processor, University of Florida Jan - Mar 2014 Developed butterfly unit RTL design for radix-2 pipelined FFT processor and RAM unit. Implemented clock gating and power gating ... - Sep 10

Representative Design

India, Kolkata, WB
... Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL. Strong understanding of Digital electronics and solid state devices. knowledge of Static Timing Analysis and Good ... - Sep 09

Verilog, VHDL, C, Physical Design, RTL synthesis/Coding

India, Vijayawada, AP
... Proficient: Experience in writing RTL Codes, FSM Based Design in Verilog HDL and Test benches in System Verilog. Good Understanding of the ASIC and FPGA Design flow and Digital Design. Worked on the Digital as well as analog and high speed VLSI ... - Sep 09

Front end Design & verification

India, Bengaluru, KA
... Cadence (Functional sim& verification, Timing sim & My Strengths: Verification, Logic Synthesis using Synopsys Design Compiler & RTL Compiler, Place & Route, Static Timing Self Confidence Analysis, Pre & Post Synthesis. Self motivated 2. Mentor ... - Sep 06

looking for a job in VLSI industry

... This has been implemented in Cadence RTL compiler, sim vision and SOC Encounter EDA tools using TSMC 180nM and 90nM process technology. MAJOR PROJECTS > Performance of VCO for 4G Applications using S parameters Group Strength:3 Here a wide band CMOS ... - Sep 04

ASIC Design Verification Engineer-Trainee

India, Bangalore, KA
... Knowledge : RTL Coding, FSM Based Design, Code Coverage, Functional Coverage, Good Understanding of ASIC/FPGA Design Flow . Scripting : Sound Knowledge of Perl . Others : Digital Fundamentals, SV Assertions ACADEMIC CREDENTIALS: . Professional ... - Sep 03

Digital design,verilog,vhdl,c,matlab

India, Chennai, TN
... Domain Knowledge : RTL Coding, Simulation, synthesis, Power Estimation, Digital Design, Implementation, NOC. Duties & Responsibilities Developing RTL Design as per the Requirements Gate Level Simulation synthesis and Timing Analysis Analyze power ... - Aug 27


Norwood, OH
... Compiler (BSD Compiler, DFT Compiler, Power Compiler), Tetramax Operating Systems: Windows, Linux/Unix, MacOS ACADEMIC PROJECTS Practical chip design of a stream cipher: RTL design of a stream cipher in Verilog followed by simulation in ModelSim. ... - Aug 26

Design Engineer

... Good Analytical abilities Flexible Quick Learner Team Player CORE COMPETENCIES Ability to understand RTL Design in Verilog RTL Simulations and Debug Ability to develop UVM based Verification environment Knowledge in SoC Verification flow TECHNICAL ... - Aug 25

Design Engineer

India, Bangalore, KA
... Verilog and VHDL HVL: System Verilog EDA Tool: Modelsim and ISE, Questa, Cadence tool Domain: ASIC/FPGA Design Flow, Digital Design methodologies Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis. ... - Aug 22

verilog,system verilog,uvm

India, Bangalore, KA
... VLSI Projects : Title: Router 1x3 – RTL design and Verification HDL: Verilog. HVL: System Verilog (UVM). EDA Tools: Questa – Verification Platform and Xilinx ISE. The router accepts data packets on a single 8-bit port called data and routes the ... - Aug 21

RTL, Verilog, FPGA/ASIC Design, Emulation, FPGA Bring up, Lab tools.

India, New Delhi, DL
... RESUME of ANIRBAN MOITRA (Msc-IC Design) : ANIRBAN First Name : MOITRA Surname Profile Snapshot: - Experience of 10 years (including Masters of 18 months) in FPGA/ASIC design and RTL coding. - Worked on synthesizable VIPs/Transactors running on ... - Aug 19

Project Design

India, Bangalore, KA
... My area of expertise is RTL design using Verilog and Verification using Verilog, System Verilog and UVM. I would like to join VLSI Industry and excel myself in the field of Design and Verification for complex ASIC/SoCs. Brief Overview Expertise in ... - Aug 18

Programming In Verilog Hdl,Vhdl,C,C++,Good Knowledge In Rtl Design.

India, Bangalore, KA
... FEBIN SEBASTIAN http://in.linkedin.com/in/febinsebastian CONTACT INFORMATION Door no 194, building number 111, munekolala, venketeshwara layout,marathahali Bangalore,560037 Ph: 08867107127 Email : acfd1a@r.postjobfree.com SUMMARY • Experience in RTL ... - Aug 15

Engineer Design

India, Bangalore, KA
... VLSI Logic design - Design flow from RTL to GDS-II generation. . Experience an EDA Tool 1. ANOLOG DESIGN CADENCE (Virtuoso Analog Design Environment): . Schematic Capture: S-Edit . Physical Layout: L-Edit . Analog Circuit Simulation using Spectre . ... - Aug 14

High School Project

India, Bangalore, KA
... 948******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Extensive experience in writing RTL models in Verilog HDL and Test benches in System Verilog and UVM > Very good knowledge in verification methodologies > ... - Aug 06

Engineer Design

India, Hyderabad, Telangana
... • 2 years of experience in RTL Design and SoC Verification using HDLs and Verification Methodologies. • Sun Certified Java Programmer with 2 years of experience in object-oriented analysis, design and development applications using C and C++. • Good ... - Aug 05