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Electrical Design Engineer

India, New Delhi, Delhi map
... in VLSI Design I gained industrial insight into various technologies & tools like Digital system, FPGA design flow from RTL design to programming device using Xilinx Tool Expertise in Synthesis, Place & Rout, Static Timing Analysis Custom IC ... - Feb 10

Engineer Project

India, Bengaluru, Karnataka map
... Pursued RTL DESIGN VERIFICATION BY SV AND UVM course. Possess comprehensive knowledge & hands on experience in Verilog HDL, System Verilog, UVM Basics Good understanding in developing Verification Environment from Specification Good understanding of ... - Feb 10

controls tech

Cocoa, FL map
James A. Holbrook **** ***** ***** Phone: 321-***-**** Cocoa, Florida 32926 E-mail: t2jwrv@r.postjobfree.com * ******* ** ********** ** industrial electronics, maintenance, C/C++ programming, controls engineering and start up of controls and... - Feb 09

Verilog,digital electronics,system verilog,uvn

India, Hyderabad, Telangana map
... CORE KNOWLEDGE Good knowledge of Verilog RTL coding, Digital Design Concepts. Good understanding of fundamentals of Transistors and circuit theory. Good knowledge of ASIC and FPGA design flow. Proficient with hands on experience in Digital Design ... - Feb 07

Design Engineering

India map
... Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog . Very good knowledge in verification methodologies. Experience in using industry standard EDA tools for the front-end design and verification. VLSI Domain Skills HDLs: ... - Feb 07

Good knowledge of Verilog, System verilog, UVM.

India map
... Summary of Qualification Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog. Knowledge in verification methodologies. Experience in using industry standard EDA tools for the front-end design and verification. ... - Feb 06

Engineer Design

India, Thiruvananthapuram, Kerala map
... AMBA AHB,APB, Ethernet,UART EDA Tools Questasim/Modelsim, NCSim, Xilinx ISE, Keil, Encounter RC Compiler Knowledge UVM/OVM,RTL coding, FSM Based Design,Simulation, Synthesis Others C/C++, 8051 programming, MATLAB, HTML & PHP Experience & Employment ... - Feb 06

Design High School

India, Bengaluru, Karnataka map
... Synthesis Tools : RTL Compiler (Cadence), Quartus II (ALTERA). Physical Design : Cadence SoC encounter, Cadence Virtuoso (Full Custom Design and Layout design). Hardware languages : Verilog HDL, system Verilog, UVM . Familiar with ASIC Design flow, ... - Feb 05

engineer

Santa Clara, CA map
... Managing codebase by SVN software, responsible for code status management and backup Bug management: tracing the bug until it is solved Outsourcing management responsible for the business of tape-out Other RTL simulation test 2013.05~Present ... - Feb 04

2.1 Years of experience with M.Tech in VLSI Design

India, Bengaluru, Karnataka map
... Understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog. Hands on experience on preparing verification plans, developing UVM and SV based test benches. Working experience in ... - Feb 04
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