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Design and Verification Engineer

India, New Delhi, Delhi map
... WORK EXPERIENCE: Having 2 years of experience as SOC Verification Engineer in Front End RTL Verification using Verilog, System Verilog with UVM. June 2013 to till June 2014, As Trainee in Incise Infotech Pvt. Ltd. June 2014 to till Now as As DESIGN ... - May 05

Design Project

India map
... Extensive experience in writing RTL Models in Verilog HDL and Testbenches in System Verilog and UVM. Good knowledge in verification methodologies. Experience in using Industry Standard EDA Tools for the front end design and verification. VLSI Domain ... - May 05

Assistant Engineer (Linux)

India map
... constructively to the company Core Competency: Good understanding of fundamentals of Transistors Good knowledge of Verilog RTL coding Good knowledge of Digital Design Concepts Implemented a VLSI and/or embedded project during my undergrad Good ... - May 04

Verilog HDL designing,FPGA implementations, testbenches verification

India, Bengaluru, Karnataka map
... Ability to work on EDA tools to synthesized various RTL schematic designs. Ability to communicate in both written and oral forms. TOOLS & COCEPTS Tools: ModelSim, Xilinx ISE Design suit 14.2, Cadence, EDK, Simulink and System Generator. Hardware ... - May 01

Digital Design,Verilog,System Verilog,Uvm Methodology

India, Bengaluru, Karnataka map
... Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog Very good knowledge in Verification methodologies(UVM) Experience in using Industry ... - May 01

Design System

India, Bengaluru, Karnataka map
... Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog Very good knowledge in Verification methodologies(UVM) Experience in using Industry ... - May 01

Design Test Cases

India, New Delhi, Delhi map
... Core Competency: Good knowledge of Verilog RTL coding. • Good understanding of Object-oriented programming (OOP) concepts. • Excellent problem solving and debugging skills. • Basic knowledge of UART, Ethernet protocol. • Skilled in HVLs such as ... - May 01

Design Test Cases

India, New Delhi, Delhi map
... Core Competency: Good knowledge of Verilog RTL coding. • Good understanding of Object-oriented programming (OOP) concepts. • Excellent problem solving and debugging skills. • Basic knowledge of UART, Ethernet protocol. • Skilled in HVLs such as ... - May 01

Engineer Development

India map
... Quick at finding, debugging, and analyzing the bugs/failures in RTL and fixing them. . Fluency with Verilog, SystemVerilog languages and OVM/UVM methodologies. . Several project cycles from concept through complete release. . Possess Sound ... - Apr 28

Manager Project

India, Bengaluru, Karnataka map
... * Expert in writing synthesizable RTL design codes using verilog. * Good knowledge in developing verification Environment using system verilog. * Strong fundamentals in Digital Electronics. * Expert in debugging and Simulation Issues. * Good ... - Apr 28
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