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Design Project

India, Kolkata, West Bengal map
... PROFESSIONAL OUTLINE With a total experience of 5 years in Teaching and FPGA DESIGN (Verilog Programmer) I have a good understanding of ASIC/FPGA Design flow, writing RTL Code design for all digital logics, and industry standard EDA tools for the ... - Jul 04

Project System

India, Mumbai, Maharashtra map
... Knowledge about RTL design, modeling and test benches using VHDL. Knowledge about gate level schematic modeling of circuits and simulation. Knowledge about system development on FPGA through EDK Tool. Knowledge about SOC (FPGA+Processor) based ... - Jul 03

Design Training

India, Bengaluru, Karnataka map
... Mobile: +91 740******* Summary of Qualifications Good understanding of the ASIC and FPGA design flow Good knowledge on writing RTL models in Verilog HDL and Testbenches in SystemVerilog Very good knowledge in verification methodologies Experience in ... - Jul 03

verilog,perl,dc compiler tool,vcs tool,cadence tool,layout designing.

India map
... The RTL is designed and simulated using Synopsys Verilog compiler simulator (VCS). Design and Verification of counters: RTL code for counters are designed and verified using Synopsys VCS. Design and verification of ALU: ALU is part of CPU which is ... - Jul 03

Digital design, verilog HDL, CMOS VLSI

India map
... The encoder and decoder are designed for the proposed scheme in RTL level in Verilog HDL. M.Tech Mini Project: Design of an efficient 3bit and 4bit Flash ADC. Tool Used: Cadence Virtuoso 6.10 tool Description: A novel attempt is made to design low- ... - Jul 02

Project Engineering

India map
... : Belgaum State : Karnataka India PROFILE Objective To work with an organization which provides me the opportunity to improve my skills, enhance my knowledge with learning and experience for career growth KEY SKILLS Knownlegde in “RTL VERIFICATION”. ... - Jul 02

Engineer Project

India, New Delhi, Delhi map
... Training under the Kanika Chuadhary (TECH) engineer pertaining to RTL designing and Verification. Projects Detail 1. AMBA APB Timer (ARM Bus) I have worked on making AMBA APB interface block that communicate with timer block and AMBA APB bus. In ... - Jul 02


India map
... SoC/IP RTL Verification Engineer for FPGA/SOC project based on UVM and using System Verilog Test benches, UVM/VMM methodologies, RTL Coding & standard protocols as I2C, SPI Strong Knowledge on – ARM, AHB/AXI, Ethernet, CPU, Graphics (DDR) Projects ... - Jul 02

design and verification enginer

India, Bengaluru, Karnataka map
... HINDPAL WM ***, Basti guzan, Jalandhar, Email: acqjqu@r.postjobfree.com Punjab,INDIA Mobile: +91 977******* Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and ... - Jul 02

Design Engineer

Tempe, AZ map
... Lawrence Clark, Spring'14 ASU -Completed RTL to GDSII format for 32-bit multi-cycle MIPS processor using TSMC 0.3 um process involving synthesis, floor planning, verification, pre-CTS, clock tree synthesis, post-CTS, buffer implementation, nano ... - Jul 01
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