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Engineer Electrical Engineering

Chicago, IL
... Highly familiar with a variety of DSP architectures Programming Languages: MATLAB, C, Java, Python Hardware Description Languages for both FPGA and ASIC development processes: VHDL RTL Design, Verilog RTL Design MS-projects LANGUAGES English, Hebrew - May 05

Digital ASIC design

India, Bengaluru, Karnataka
... c, Verilog, VHDL, Latex, Assembly programming, R statistical language { Tools: Cadence Virtuoso, Cadence Spectre, Encounter RTL compiler, Synopsys Design compiler, Xilinx, ngSpice, pSpice, LabView, Kiel, Modelsim, Magic Layout Editor, MATLAB, ... - May 04

Design Engineering

India, Bengaluru, Karnataka
... Karnataka Secondary Education Examination Board, Bangalore March 2007 SSLC 77.92% TECHNICAL SKILLS EDA Tools & Simulators : Cadence tools: Virtuoso Schematic Editor, NC-Verilog Simulator, RTL Complier, Layout XL (basics), Encounter, Assura(basics). ... - May 02

Project Engineer

India
... RTL Synthesis: RTL Compiler. A) Semi Custom - RTL Synthesis: RTLCompiler. Physical Design: SoCEncounter . B) Custom Design - Schematic Editor, Spectre. Layout Editor, Cadence Assura. Cadence Virtuoso (6.1.3.5 XL), SOCEncounter. TRAINING: A Cadence ... - Apr 30

Design Project

India, Bengaluru, Karnataka
... Knowledge on Digital Design Concepts, RTL Design. Experience in using industry standard EDA tools for the front-end design and verification. KEY SKILLS HDLs : Verilog EDA Tools : Synopsys VCS, Design Compiler Domain : ASIC design flow, Digital ... - Apr 28

Design Project

India, Bengaluru, Karnataka
... Knowledge on Digital Design Concepts, RTL Design. Experience in using industry standard EDA tools for the front-end design and verification. KEY SKILLS HDLs : Verilog EDA Tools : Synopsys VCS, Design Compiler Domain : ASIC design flow, Digital ... - Apr 28

Design Engineer Electrical Engineering

Syracuse, NY
... Completed RTL to GDSII flow. Achieved 28% to 30% reduction in leakage current by plaguing the industry by a radical new technique of insertion of a sleep transistor to a cell. Perl Developer, Freelancer May 2014–Aug 2014 Library Cataloger: Designed ... - Apr 27

work in any envirnment

India, Hisar, Haryana
... The design involves RTL development of Data-Path, Control-Path and Processing Blocks for lifting-based Forward DWT Processor in Verilog HDL. The project is aimed at efficient hardware architecture for the algorithm, synthesis and timing verification ... - Apr 25

Engineer Design

Los Angeles, CA
Parikshit Deshpande **** * ******* *****, *****: (562)***-**** Apt 138, Long Beach, CA 90815 Email: acuhnm@r.postjobfree.com Objective Seeking a challenging entry level position that utilizes and enhances my skills in IC layout, ESD/latch up, RTL/DV ... - Apr 24

State University Design

San Jose, CA
... of processor which include read/write, add/subtract, and load/store • Simulated and synthesized Verilog code, with generating RTL level design, in Synopsys VCS using UNIX environment and Perl script 16-bit Multiplier using only one 4-bit adder, San ... - Apr 22
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