rtl resumes

Design Engineer

... Good Analytical abilities Flexible Quick Learner Team Player CORE COMPETENCIES Ability to understand RTL Design in Verilog RTL Simulations and Debug Ability to develop UVM based Verification environment Knowledge in SoC Verification flow TECHNICAL ... - Aug 20

RTL, Verilog, FPGA/ASIC Design, Emulation, FPGA Bring up, Lab tools.

India, New Delhi, DL
... RESUME of ANIRBAN MOITRA (Msc-IC Design) : ANIRBAN First Name : MOITRA Surname Profile Snapshot: - Experience of 10 years (including Masters of 18 months) in FPGA/ASIC design and RTL coding. - Worked on synthesizable VIPs/Transactors running on ... - Aug 19

Project Design

India, Bangalore, KA
... My area of expertise is RTL design using Verilog and Verification using Verilog, System Verilog and UVM. I would like to join VLSI Industry and excel myself in the field of Design and Verification for complex ASIC/SoCs. Brief Overview Expertise in ... - Aug 18

Programming In Verilog Hdl,Vhdl,C,C++,Good Knowledge In Rtl Design.

India, Bangalore, KA
... FEBIN SEBASTIAN http://in.linkedin.com/in/febinsebastian CONTACT INFORMATION Door no 194, building number 111, munekolala, venketeshwara layout,marathahali Bangalore,560037 Ph: 08867107127 Email : acfd1a@r.postjobfree.com SUMMARY • Experience in RTL ... - Aug 15

Engineer Design

India, Bangalore, KA
... VLSI Logic design - Design flow from RTL to GDS-II generation. . Experience an EDA Tool 1. ANOLOG DESIGN CADENCE (Virtuoso Analog Design Environment): . Schematic Capture: S-Edit . Physical Layout: L-Edit . Analog Circuit Simulation using Spectre . ... - Aug 14

High School Project

India, Bangalore, KA
... 948******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Extensive experience in writing RTL models in Verilog HDL and Test benches in System Verilog and UVM > Very good knowledge in verification methodologies > ... - Aug 06

Engineer Design

India, Hyderabad, Telangana
... • 2 years of experience in RTL Design and SoC Verification using HDLs and Verification Methodologies. • Sun Certified Java Programmer with 2 years of experience in object-oriented analysis, design and development applications using C and C++. • Good ... - Aug 05

Verilog,System Verilog

India, Bangalore, KA
... Projects: Router 1x3 -- RTL design and Verification Team Size: 2 Role: Designed the model and verify its application. Responsibility: Architected the design and described the functionality using Verilog HDL. Architected the class based verification ... - Jul 30

Front End Design Engineer

... Work Experience:- Organization : - STMicroelectronics, Noida, Uttar-Pradesh : - Intern (12th July 2013 till 27th June 2014) Role Responsibility : - Memory behavioral coding, Validation of RTL, Test Patterns of Chip and making Tool of Automatic Test ... - Jul 25

Pvt Ltd Project

India, Bangalore, KA
... Systems: Windows, UNIX Tools: Cadence basics, Xilinx, VCS simulator, Novas simulator, ModelSim, MS Tools Area of Interest: RTL Design, Circuit Design, VLSI Verification and Validation, DFT M.Tech PROJECT DETAILS – Carried out at Intel India Pvt Ltd ... - Jul 25

Design Project

India, Mumbai, MH
... Visakhapatnam, Mobile: +91 903******* Andhrapradesh, India - 530027 +91 855******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog. ... - Jul 16

Design Power

United States
... Verilog RTL; VHDL; Basic Perl. Industrial Experience / Projects Engineering Intern at Maxim Integrated Product Corp. Summer 2013 Worked on Power Management Integrated Circuit(PMIC) Products in Design, Application and Test Enhanced IC related design ... - Jul 14

Senior ASIC Design/Verification Engineer

Malaysia, Bayan Lepas, Penang
... RTL design. . Proficient in developing Testbench/BFMs (OVM/SystemVerilog). . Assertions/Functional Coverage. . Testplan/Testcase development. . Hands on in both ASIC/FPGA design flow. . Familiar with low power design concepts, like multiple power ... - Jul 14

ASIC design and verification engineer

... NIKITA BHANDARI aceyf2@r.postjobfree.com +**- ***** ***** PROFESSIONAL EXPERIENCE SUMMARY Around 2 years of experience in RTL Design and Verification Proficiency in Verilog and SystemVerilog languages Worked on Code and Functional Coverage analysis ... - Jul 13

Design Engineering

India, Bangalore, KA
... Udaya Kumar H # *** **** ****** A M Palya Siragate Tumkur Karnataka Email: aceyev@r.postjobfree.com India - 572106 Mobile: +91 962******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Experience in writing RTL ... - Jul 13

RTL Developer(VLSI)

India, Bangalore, KA
... H no :- 6 -77, Knowledge on RTL Design, FPGA/CPLD implementation, ADC, DAC, Bayana palle village, 8051 Microcontroller. Obana palle Post, Knowledge on Verilog/VHDL HDL language, Embedded C programming, Rly Kodur Mandal, Kadapa Dist, Matlab Simulink, ... - 2013 Dec 30