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Senior Quality Engineer

United States map
... Participated in Sanity Testing, Smoke Testing, Regression Testing, Campaign Testing, Reception Control Testing, and RTL Testing. Performed test cases of Performance, Function, Duration, Interoperability, Interactivity, Stress, IOT, Usability, ... - Oct 12

RTL design and verification

India, New Delhi, Delhi map
... Extensive experience in writing RTL Models in Verilog HDL with all coding styles and flat and layered Testbenches in System Verilog. Expertise in verification methodologies like UVM, OVM. Experience in using Industry Standard EDA Tools for the front ... - Oct 07

Project Engineering

India, Hyderabad, Telangana map
... Tools: MATLAB, Multisim, Cadence - NC, Spectre, Virtuoso ADE, Assura, Encounter RTL Compiler, SOC Encounter CERTIFICATIONS 1. Certified in Physical design through Cadence VLSI Certification Program (CVCP) PROJECTS 1. Advance Peripheral Bus (APB) ... - Oct 07

Design Engineering

India, Gurgaon, Haryana map
... SrikanthGaddam Email:acrzon@r.postjobfree.com Mobile:+919989584699 Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog. Very good knowledge in ... - Oct 06

Security Engineer

Fairfield, IA map
... 2007/2010, Scripting Languages: Python, Shell scripting, VB script Embedded Programming: VHDL language on Xinlinx (RTL Schematic & Simulator) Architecture: J2EE (Frameworks: Struts & Hibernate, JPA), XML, Joomla1.6 + components and modules, Ajax. ... - Oct 06

Design Project

India, Bengaluru, Karnataka map
... Entire design is carried out on TSMC submicron 180nm process technologies 3)TITLE: RTL coding for AMBA-APB Protocol and verification of the protocol using a layered test bench . DESCRIPTION: AMBA-APB (Advanced Peripheral bus) is an on-chip ... - Oct 06

Design High School

India, Kanpur, Uttar Pradesh map
... Percentage Score: 88.80% TECHNICAL SKILLS Languages C language, Core JAVA, SQL, Perl Scripting, Verilog HDL, TCL Tools Xilinx: ISE, Chipscope, XPE Cadence: Virtuoso, Encounter, LVS LASI Skills ASIC Design, Digital Design, Low Power design, RTL ... - Oct 06

VLSI Design. Top Skills:Cadence Virtuoso, System Verilog, UVM, Verilog

India, Bengaluru, Karnataka map
... 6.Cadence simulation and synthesis tools : SimVision, Encounter RTL Compiler. PROJECTS M-TECH PROJECTS 1)Design of Router 1X3 using Verilog HDL and also verified the design using Verilog HDL and UVM methodology. 2)Low Power Test Pattern generator ... - Oct 01


India, Salem, Tamil Nadu map
... VLSI FUNDAMENTALS FPGA Flow ASIC Flow HDL LANGUAGES Verilog HDL VHDL TOOLS HANDLING RTL simulation - ModelSim-Altera 6.4a RTL synthesis - Altera Quartus II 9.0, Xilinx ISE Design Suite 12.1 FPGA VALIDATION Altera - Cyclone II Xilinx - Spartan 3, ... - Sep 30

Design Power Plant

Highland Park, NJ map
... • Hands on experience in Logic design: RTL design (VHDL, Verilog), verification, Synthesis, static timing analysis (STA), testbench, place and route, physical verification (DRC/LVS/ERC). • Experience in circuit design (Analog/Digital/RF): Circuit ... - Sep 28
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