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Design Engineering, SystemVerilog, HSPICE, STA, Perl, Cadence

Phoenix, AZ map
... Experienced in RTL Design and verification, synthesis, Layout optimization, HSPICE simulations and Static Timing Analysis. Worked on full-custom designs and automated designs including Register Files and L1 Cache for low power constraints and 32-bit ... - Apr 01

Engineering Design

Canada, Mississauga, Ontario map
... Created test benches, test codes in Verilog, VHDL, C, C++ & RTL Programming for verification of SOC audio / video decoders & synchronizers; as per global industry standards; such as AC3 encoding / decoding, MPEG audio, SIF, audio transmission, audio ... - Apr 01

Project Development

India, Bengaluru, Karnataka map
... Operating frequency of the design 225 MHz Role: Architecture designing of controller and RTL coding by using VHDL. 2. Implementation 32-Bit R.I.S.C Processor Description: The aim of the project is to implement the R.I.S.C processor of Von Neumann ... - Mar 29

Project Design

India, Bengaluru, Karnataka map
... Also,the main motive is to develop an efficient UPF at RTL level such that power dissipation can be reduced by atleast (20-30)%.The main work in this project was to import the upf file to the testbench and verify all the power managements. The power ... - Mar 29

Design Engineer

Raleigh, NC map
... Designed a hardware using Verilog RTL to process a series of input images (640 480 pixels) to obtain an equalized image at the output, which was then optimized for delay area product. The hardware was simulated /verified using Modelsim and ... - Mar 26

verilog,perl,dc compiler tool,vcs tool,cadence tool,layout designing.

India map
... The RTL is designed and simulated using Synopsys Verilog compiler simulator (VCS). • Design and Verification of counters RTL code for counters are designed and verified using Synopsys VCS • Design and verification of ALU ALU is part of CPU which is ... - Mar 22

Verilog,RTL coding,Verification,C,C++

India, New Delhi, Delhi map
Joseph Chacko Current Address: Ph(mobile) :( +**)999******* Kripa Appmts, Vaishali, Email: acotpt@r.postjobfree.com Sector-6, Plot No:133, G-1, Ghaziabad, UP, 201010 Objective: Seeking a position to utilize my skills and abilities in the reputed... - Mar 21

Management Engineering

San Jose, CA map
... Generate cycle accurate execution result 16-Bit RISC Processor ( VLSI Design: Schematic, RTL, Layout )? 1.Designed instruction set follows MIPS architecture and wrote an assembler in python 2.Designed, simulated/tested 16-bit RISC and done the RTL ... - Mar 20

Engineer Design

Ames, IA map
... For the algorithm development purpose as an RTL code design for digital video chips, the decoder that consists of both Y/C separation comb filters and GENLOCK PLL, chrominance de-modulators, two- dimensional band-limit filters, and ITU-656 formatted ... - Mar 20

Design Engineer Manager

San Francisco, CA map
... SUMMURY: 20+ years experience with ASIC design including specification, RTL coding, simulation, synthesis, verification and bring-up. REFERENCES: Available upon request ... - Mar 17
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