Project Experience Engineer System Design Development

India, Bangalore, KA
... FPGA design flow from RTL design to bitgen xilinx tool flow. Involved in Development of class based Arbiter verification in System Verilog. Involved in Development of Test bench environment for various projects in UVM. Knowledge of JTAG protocol. ... - May 23

Engineer Developer Electrical Engineering Design

United States
... Keen on facing challenges Can turn algorithms, protocols into efficient Enjoys problem solving, hardware architectures, RTL code HDL coding, debugging Successful experience of team work and Attentive to details meeting tight deadlines Proficient ... - May 23

Sr. Technical Recruiter Full-life cycle recruitment

SF, CA
... Staffing Program Managers, Certified Project Managers, Process Improvement, ITIL, Six Sigma, Agile Methods, SCRUM Masters, design engineers with ASIC, Verification, SRAM, RTL, DFT, Synopsis, FPGA, logic, Board level, physical design, IC design, and ... - May 20

Engineer Project Career Objective Design Experience

India, Bangalore, KA
... Ltd as Verification engineer from September 2011 to till date Responsibilities: Verilog RTL Coding, Functional Testbench, Randomized Testbench, Timing Closure, DFT(ATPG/BIST), Whole chip top level integration, Cowork with APR(Floorplan, clock tree ... - May 14

Entry Level Design Engineering Engineer Assistant

Austin, TX
... ABDULLAH AL OWAHID Cell: 205-***-**** Email: abux9q@r.postjobfree.com, abux9q@r.postjobfree.com Location: 5001 Convict Hill Rd, APT 617, Austin, TX-78749, USA OBJECTIVE: Entry level position in RTL design, physical design, circuit design, computer ... - May 13

Engineer Design Management Experience Development

Woburn, MA
... Core strengths in Multimedia decoder architecture and RTL design and verification, ASIC and design FPGA IP/RTL modeling in C SOC modeling Graphics and video processing Memory controller design, DDR Embedded Firmware Windows system/platform debug ... - May 10

Engineer Design Sales Manager Project Engineering

Dallas, TX
... Documented and designed Verilog RTL with DFT components for digital VCO calibration and programmable clock dividers for high-speed mixed- signal chips running up to 1.2 GHz. . Synthesized design with DFT SCAN chains using Synopsys DC and Cadence RC ... - May 09

Experienced Retail Manager Seeking Full Time Position

Asheville, NC
... Supervise the Merchandise Team Leader, Operations Team Leader, Receiving Team Leader RTL and fifteen associates in operations, receiving and. Directs the Manager-on-Duty MOD program ensuring daily duties are performed efficiently, effectively, and ... - May 08

Results-oriented Engineer

SF, CA
... Digital Design flow for small circuit design group Lead both consultants and employees to the completion of many projects Fremont, CA Fall 98 Senior Digital Design Engineer I was responsible for RTL Design and Verification of Audio Processors. ... - May 08

Design Career Objective Engineer Project Engineering

India, Bangalore, KA
... : Coverage Driven Verification, Assertion Based Verification Knowledge : Digital Design, RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV, Telecom protocols like GSM, CDMA, etc... ... - May 08

Engineer Design Development Experience Project

India, Bangalore, KA
... Expertise in High speed FPGA based RTL implementation using VHDL, functional verification, timing closure, debugging and board bring-up . Expertise in Board level to system level integration testing . Experience in high speed board design and PCB ... - May 06

Senior Radar Systems Engineer

Orlando, FL
... Planned and executed a successful "bit for bit" compare against RTL (Verilog/VHDL) output . Developed a model object library, which included customized "C-coded" blocks . Incorporated a modular and hierarchical object block design into the simulator ... - May 04

Engineer Design Electrical Engineering Experience

San Jose, CA
... Verilog simulator Implementation Jan - May, 2011 Designed and implemented a Verilog-based RTL simulation software using C++, with lexical and syntactic analysis, netlist construction and logic simulation functions included. 10-T full-adder low power ... - May 03

Verilog, VHDL, Digital Logic Design, Assembly Language, Microprocessor

India, Hyderabad, AP
... This project involves design specifications, RTL design, test bench coding and verification and Implementation of design on Xilinx Spartan-3E device. Personal Profile Name : Ashokchakravarthi Muppa Father's Name : M. Omkaram Date of Birth : 19-08 ... - May 01

Customer Service Management Sales Manager Developer

New York, NY
... Monitored daily changes to the Restricted Trading List (RTL) on an hourly basis by consulting the Desk Parent Issuer and Ultimate Issuer listings. . Assisted in the Canadian Hedge Fund Sales reporting for 2005 by compiling spreadsheets for all funds ... - Apr 28

Engineer Design Career Objective Project System

India, Bangalore, KA
... I'm deeply interested in working with Digital Design, RTL coding, FSM Design and its simulations, verification using UVM and VLSI design. Qualifications • M.Tech (VLSI Design)- from ASE Bangalore, affiliated to Amrita Vishwa Vidyapeetham University ... - Apr 27

Project Career Objective Design Engineering Software

India, Bangalore, KA
... Core Competency: Good understanding of fundamentals of Transistors and circuit theory Comprehensive knowledge of the methodologies and applications of advanced verification tools Good knowledge of Verilog RTL coding and Digitial Design Concepts Good ... - Apr 27

Career Objective Design Management Project Experience

India, Pune, MH
... EDUCATIONAL QUALIFICATION Technical Knowledge Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog Experience in using industry standard EDA tools for the front-end ... - Apr 26

Engineer Project Software Customer Data Quality Assurance

South Korea, Seoul
... Hardware team receive requirements, they implement hardware simulation by RTL and release ".sof file". We, software team used that ".sof" file, load into MPS board. Base on what HW team implemented, which modules they implemented (NOR Flash, SCIF ... - Apr 21

Network Engineer

Austin, TX
... • Performed RTL verification of Lucent High Order Switch for SONET-based networks. • Performed RTL verification, using tests written in C, of Bay Networks T1/DS-1-to-OC12 SONET/ATM router. LANCAST, INC. Nashua, NH Hardware Engineer 1997 • Designed ... - Apr 18