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FPGA/RTL Design Engineer

India, Bengaluru, Karnataka map
... Profile M-Tech – VLSI & Embedded Systems B-Tech – Electronics & Communication Engineering Synopsis of Experience 2 years of experience in front end RTL design, development and verification for target FPGAs (Xilinx 7 series & Actel) Academic Record ... - Jul 27

Test/ Validation Engineer

Portland, OR map
... Key Skills: * Expertise: DFT, Analog & Mixed Signal Circuit, PLL, Bluetooth, RF/High-Frequency Circuit, Optical Inter-Connect * Tools: TPIE, Primetime, Debussey, Netview, Cadnav, Opus * Languages: Perl, C/C++, Assembly, RTL, System Verilog, VHDL * ... - Jul 27

Engineer Design

India, Maharashtra map
... Proficient in RTL design, simulation and synthesis using Xilinx ISE™ Knowledgeable in CMOS VLSI design, Verilog RTL coding, ASIC front end/back end design, Simulation, Synthesis, MAP and Place & Route. Knowledgeable in Physical design flow. ... - Jul 27

Design Engineer Project

India, Nellore, Andhra Pradesh map
... Experience Summary Currently working as a RTL Design Engineer in Spiro Solutions Pvt. Ltd, Chennai since June-2013. Expertise in Design and Development of modules for the ASIC Applications. Contributing to the design, development, testing and ... - Jul 25

VLSI design & Embedded system Verilog, SystemVerilog, Embedded C

India, Ambavaram, Andhra Pradesh map
... for Post-graduation project titled “Coverage Driven Constraint Random Verification using SystemVerilog” During my tenure as an Intern I have equipped with the respective skill set as follows Experience in RTL Design and Synthesis using Verilog. ... - Jul 24

ASIC, verification, DFT,RTL,Cadence,OVM

India, Bengaluru, Karnataka map
#***, ********** *****, Cheyyar-******, Thiruvannamalai Dt, Tamil Nadu. Mobile: +91-959*******, +91-978*******, Email:acqwli@r.postjobfree.com Dinesh Kumar.B Career Objective: A Design and Verification Engineer position in an organization seeking... - Jul 24

verilog, System Verilog, UVM,digital electronics.

India, Bengaluru, Karnataka map
... Verified the RTL using Verilog and UVM test benches. Trace Buffer Observation Via Selective Data Capture Using 2-D Compaction Technique For Post Silicon Debug Role: Team leader. Environment: Verilog HDL. Project Description: The main aim of this ... - Jul 24

Project Test Cases

India map
... Hands on experience with Modelsim and Questasim Expertise in RTL coding,simulation and synthesis ACADEMIC PROFILE: B.Tech in Electronics and communication from Sri Sivani College of Engineering and Technology with 54.1% (2007-14). Intermediate from ... - Jul 24

C,C++,Vhdl,Verilog,System Verilog,Ovm,Uvm,Perl,Sta,Abv,Ip Protocols

India, Bengaluru, Karnataka map
... Router 1x3 RTL Design & Verification HDL: Verilog TB Methodology: UVM EDA Tools: ISE and Questasim Description: The router accepts the data packets on a single 8 bit port and routes them to one of the three output channel0, channels1 and channel2. ... - Jul 24

Web Developer Part Time

Trenton, NJ map
... Projects Undertaken DESIGNING OF CROSSTALK AVOIDANCE CODE (CAC) SCHEMES: NOV 2014(RIT) Three CAC schemes were implemented using Verilog RTL Coding, in order to reduce the energy dissipation in Network-On-Chip (NoC) designs. The RTL coding was tested ... - Jul 23
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