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Design Assistant

India, New Delhi, Delhi map
... Experience in writing RTL models in Verilog HDL, VHDL and Test benches in Verilog and SystemVerilog. Very good knowledge in verification methodologies. Experience in using industry standard EDA tools for the front-end design and verification. Good ... - Dec 17

Engineering High School

India, Bengaluru, Karnataka map
... ASIC and FPGA design flow Complete knowledge of verilog,system verilog,advance system verilog Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog Very good knowledge in verification methodologies Experience in ... - Dec 16

VLSI design and Embedded System

India map
... Core Competency: • Good understanding of fundamentals of Transistors and circuit theory • Good knowledge of Verilog RTL coding • Good knowledge of D igital Design Concepts • Good exposure to technology by undergoing additional t raining in V LSI and ... - Dec 14

Training Project

India, Navi Mumbai, Maharashtra map
... National and International Traffic migration from RTL Roamware to RCOM Roamware server (Changing definitions at STP end). Analyzing various Roamware products traffic reports and fixing the network accordingly. RCOM CDMA Project: Responsible for ... - Dec 11

Embedded software / firmware Engineer

Poway, CA map
... Work with ASIC developers on RTL simulation of ASIC circuits. . Using DCD 8051 core IP in ASIC design. . MDIO communications to MAC and PHY devices. . I2C communications for primary and secondary boot loader. . XUAI / RXAUI interface. . C simulation ... - Dec 11

Engineer Design

Canada, Calgary, Alberta map
... Architecture design requirements (from modeling -> floating point -> fix point -> RTL). Xilinx Virtex 5 . CQS Egress FPGA to provide QoS, DMA, MAC protocol processing for Lucent Broadband ATM GX 550 BIO CP. Xilinx Virtex 5 ASIC/FPGA Designer Nortel ... - Dec 11

Office Manager

India, Thiruvananthapuram, Kerala map
... Ltd (RTL) Office cum Sales Coordinator. * May 2007 - July 2012 - THR GROUPS (Corp. Off.) Front Office Manager. * February 2005 - April 2007 - K.I.M.S. Councilor and Co-ordinator. * January 2004 - December 2004 - WFTQS. BPO Quality Controller. * ... - Dec 11

Embedded Software Engineer

Escondido, CA map
... Used HLS (High Level Synthesis) tools to render C++ (incuding System C library) to a digital hardware description language [Register Transfer Level, (RTL)]. The generated hardware implements the time domain horizontal filter for h.265 video ... - Dec 10

Engineer Design

India map
... v Front-End Design and Verification of small ASIC based designs using Verilog Adroit Solutions: § RTL coding of small building blocks of ASICs such as memory controller, FIFO etc. In ModelSim/Questa Sim using Verilog and synthesizing the codes to ... - Dec 10

Project Design

India, Ambavaram, Andhra Pradesh map
... Experience with RTL & Behavioral coding with Verilog. Experience in writing test benches using Verilog. Experience with synthesis and optimization of Verilog code. Simulation tool experience with Mentor Graphics Questa sim, Xilinx ISE. Experience ... - Dec 05
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