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Project Engineering

India, Chennai, TN
... • Good knowledge of Verilog RTL coding. • Good knowledge of Digital Design Concepts. • Good knowledge of Analog Design. • Education Examination University/School Year Class Obtained Percentage M.Tech in VLSI R.V. College of Pursuing First class 67% ... - Oct 19

Engineer Quality Assurance

Chicago, IL
... Specifications of Electronic Equipment, Technical Report Writing, Testing Theoretical Design Aspects, Using Measuring Equipment, Communicating on Technical Level with Other Engineers, RTL Design, Calculus and Mathematical Modeling Accomplishments 1. ... - Oct 18

Design Engineering

... • Experience in writing RTL models in Verilog HDL and familiar with System Verilog and UVM. • Knowledge of Digital electronics and CMOS fundamentals. ACADEMIC QUALIFICATIONS: DEGREE/ EXAMINATION UNIVERSITY/BOARD YEAR OF PASSING MARKS B. Tech ... - Oct 18

Project Engineering

... +91 973******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM > Very good knowledge in verification methodologies > ... - Oct 17

Design Engineer

... OVERVIEW Good understanding in Digital logic design & Electronics fundamentals • Good understanding of the ASIC/FPGA design flow • Experience in Verilog HDL to write synthesizable RTL, self-checking test benches& • Test benches in system Verilog ... - Oct 16

Good Knowledge in System Verilog, Verilog & UVM.

India, Bengaluru, KA
... Projects: Router 1x3 -- RTL design and Verification Team Size: 2 Role: Designed the model and verify its application. Responsibility: • Architected the design and described the functionality using Verilog HDL. • Architected the class based ... - Oct 16

Engineer Project

India, Hyderabad, Telangana
... July 2012 to September 2012 Role : UPF checks on large RTL and NETLIST designs. Environment : Linux(redhat) Tool : Monet (synopsys) Tool : Spyglass,DC Compiler Projects Undertaken at MCIS Manipal 1) TSPC LATCHES AND FLIPFLOPS CHARACTERIZATION ... - Oct 16

Vlsi Rtl Design And Testbench

India, Agra, UP
... Project4 : Clock Gated Low Power Sequential Circuit Design Description: In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. ... - Oct 14

Engineering Service

India, Bengaluru, KA
... > Working skills on RTL design and Static Timing Analysis . > Knowledge on FPGA, ASIC and Microprocessors. > Good at CMOS technology and Analog circuits. Projects > Implementation of CANNY EDGE DETECTION IN FPGA. Tools used : MATLAB R2013a : XLINIX ... - Oct 13

Vlsi Design,Verilog,System Verilog, I2c, Vip, Eda, Modelsim, Gvim,Rtl

India, TN
GOKULAKRISHNAN.S Email Id : acgck0@r.postjobfree.com */179,singarapettai st., Thirumani, Contact : +91 848******* Thiruvannamalai - 604504. CAREER OBJECTIVE: Aspiring for a career that places me in a challenging position and learning-oriented... - Oct 12

Project Data

India, Hyderabad, Telangana
... Experience in RTL Design using VHDL,Verilog. Developed OVM Test bench environments for different modules. Experience in Functional Verification using constraint random and coverage driven methodology. Involvement in complete Functional verification ... - Oct 10

Hardware / software Engineer

Austin, TX
... Simulation-based verification of RTL design with special emphasis on IO interface. . Discovered bugs, characterized them, offer appropriated solutions, and regressed bugs. . Reviewed project specifications; generated test plans, test cases, and ... - Oct 09

Engineer Design

... I'm deeply interested in working with FPGA, ASIC, Digital Design and RTL coding. Employment Focuz innovations Pvt. Ltd, Mamangalam, cochin, Kerala (13/9/2013 to till date) (VLSI- Embedded Engineer) Maven Silicon Softech Pvt Ltd, Bangalore (23/1/13 ... - Oct 09

Project Engineering

... % Programming ThroughVHDL, RTL Design Using Verilog, Basics Of Programming-Languages : Verification Using System Verilog, Basics Of PERL Scripting Language, Basics of C programming. Operating Systems : Windows XP/7, Vista. Hardware Skills ... - Oct 09

Customer Service High School

Houston, TX
... HAIRSTYLIST, 01/2011 to 03/2012 RTL IMAGE HAIR STUDIO- 3910 Fairmont Pkwy Hairstylist, answered phones, set up appointments, keep my station clean and greet customers EDUCATION High School Diploma:2004 CESAR CHAVEZ HIGH SCHOOL- 8501 Howard Dr. ... - Oct 08

Area of Interests- Physical Design, EDA Tool Designing, layout

India, New Delhi, DL
... Enterprise Linux v5.4 & v6.3 1 4 Scripting languages Shell, Perl/TK Tools & Technologies Cadence Virtuoso, SoC Encounter, NC-SIM, RTL Compiler, Xilinx ISE & System Ed, Tanner (L-Edit, S- Edit, LT-Spice), TCAD, Mentor Graphics (Questa Sim) Software ... - Oct 08

physical design engineer

India, Hyderabad, Telangana
... (Synthesis) VCS(Functionality and simulation checking) Cadence: Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis Encounter Timing System –Static Timing Analysis and Crosstalk Analysis RTL Compiler- Logic Synthesis. ... - Oct 07

Physical Design(Floor plan,Power plan, Placement, CTS, Place&Rute)

India, Bengaluru, KA
... • • Verilog Cmos • • System Verilog Digital Design • Perl • Verilog • Cadence Virtuoso • System Verilog • NC Sim • FPGA • RTL compiler • Synthesis 1 • • Encounter DFT • Place & Route Technical Proficiency • Post Graduate Diploma in VLSI Design & ... - Oct 06

Power Pvt Ltd

India, Bengaluru, KA
... Skills Cadence RTL compiler, Cadence SOC Encounter, Synopsis ICC, STA VLSI Projects Profile Project # 1 : RTL to GDS II of low power application FIR Filter, Tools Used : . Cadence RTL compiler for Synthesis and DFT. . Cadence Encounter for Floorplan ... - Oct 06

Design Engineer

India, Bengaluru, KA
... Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog. Experience in using industry standard EDA tools for the front-end design & verification and Physical Design. Experience with Altera development tools. 4. TOOLS & ... - Oct 04
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