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Verilog,System Verilog

India, Bangalore, KA
... Projects: Router 1x3 -- RTL design and Verification Team Size: 2 Role: Designed the model and verify its application. Responsibility: Architected the design and described the functionality using Verilog HDL. Architected the class based verification ... - Jul 30

Front End Design Engineer

India
... Work Experience:- Organization : - STMicroelectronics, Noida, Uttar-Pradesh : - Intern (12th July 2013 till 27th June 2014) Role Responsibility : - Memory behavioral coding, Validation of RTL, Test Patterns of Chip and making Tool of Automatic Test ... - Jul 25

Pvt Ltd Project

India, Bangalore, KA
... Systems: Windows, UNIX Tools: Cadence basics, Xilinx, VCS simulator, Novas simulator, ModelSim, MS Tools Area of Interest: RTL Design, Circuit Design, VLSI Verification and Validation, DFT M.Tech PROJECT DETAILS – Carried out at Intel India Pvt Ltd ... - Jul 25

Design Project

India, Mumbai, MH
... Visakhapatnam, Mobile: +91 903******* Andhrapradesh, India - 530027 +91 855******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog. ... - Jul 16

Design Power

United States
... Verilog RTL; VHDL; Basic Perl. Industrial Experience / Projects Engineering Intern at Maxim Integrated Product Corp. Summer 2013 Worked on Power Management Integrated Circuit(PMIC) Products in Design, Application and Test Enhanced IC related design ... - Jul 14

Senior ASIC Design/Verification Engineer

Malaysia, Bayan Lepas, Penang
... RTL design. . Proficient in developing Testbench/BFMs (OVM/SystemVerilog). . Assertions/Functional Coverage. . Testplan/Testcase development. . Hands on in both ASIC/FPGA design flow. . Familiar with low power design concepts, like multiple power ... - Jul 14

ASIC design and verification engineer

India
... NIKITA BHANDARI aceyf2@r.postjobfree.com +**- ***** ***** PROFESSIONAL EXPERIENCE SUMMARY Around 2 years of experience in RTL Design and Verification Proficiency in Verilog and SystemVerilog languages Worked on Code and Functional Coverage analysis ... - Jul 13

Design Engineering

India, Bangalore, KA
... Udaya Kumar H # *** **** ****** A M Palya Siragate Tumkur Karnataka Email: aceyev@r.postjobfree.com India - 572106 Mobile: +91 962******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Experience in writing RTL ... - Jul 13

RTL Developer(VLSI)

India, Bangalore, KA
... H no :- 6 -77, Knowledge on RTL Design, FPGA/CPLD implementation, ADC, DAC, Bayana palle village, 8051 Microcontroller. Obana palle Post, Knowledge on Verilog/VHDL HDL language, Embedded C programming, Rly Kodur Mandal, Kadapa Dist, Matlab Simulink, ... - 2013 Dec 30