Rtl Resumes

Sign in
Search for: Jobs   Resumes

Get new resumes like this by email Resumes 1 - 10 of 1786

VLSI Engineer

India, Bengaluru, Karnataka
... Experience in RTL Design verification and validation, test cases and testbench development Good Knowledge of VHDL and Verilog Good Knowledge of MATLAB /Simulink Knowledge of Assembly languages programming, System Verilog HDL and UVM Programming ... - Jul 21

Computer Science Engineering

... SQL, MySQL, PostgreSQL, MongoDB, HyperSQL, NoSQL, C, C++, C#, Python, JavaScript, JSON, HTML, XML, MIPS, Assembly, Verilog, RTL, MATLAB, R, Linux/Windows, OpenGL, Unity3D, Apache HTTP Server, Photoshop, MS Office, Vuforia, AllJoyn, Leap Sensor, ... - Jul 21

ASIC Verification Engineer RV-VLSI Design Center

... Core Competancy Proficient knowledge of the ASIC Flow from the logic design to RTL Synthesis Good Working Knowledge of Protocols like SATA Link Layer AMBA APB UART and SPI Expertise in writing testbench in UVM Methodology and System Verilog language ... - Jul 15

Engineer Computer Science

Irvine, CA
... Skills: Python, Java, UNIX, SQL, C, Android, Tcl Work Experience Engineer II, Broadcom, Irvine CA 7/2013-Present • Leading project to design an SQL database for managing IOs and generating RTL for WLAN radios. • Created a Python library to parse ... - Jul 12

M.tech With 11 Months of Experience as VLSI RTL Design Engineer

... Profile Summary: 09 months of experience as VLSI RTL Developer, working at Data Point Info Solutions Pvt. Ltd, Hyderabad from August 2015 to till date... Programming expertise in Verilog HDL, VHDL, C, and Java. Good communication, written and ... - Jul 11

VLSI Design verification(Fresher)

India, Bengaluru, Karnataka
... Experience in writing RTL models in verilog. Good understanding of object oriented programming (OOP) concepts. Skilled in HVLs such as system verilog. Good knowledge of Digital Design concepts and FSM fundamental concepts. Basic knowledge of UART, ... - Jul 09

Design Data

Los Angeles, CA
... Synthesized the RTL design to gate level netlist using Synopsys DC. Static Timing Analysis was performed using PrimeTime. Performed Logic Equivalence Checking using Cadence Conformal, APR and CTS using Cadence SOC Encounter. Language: Verilog CAD ... - Jul 08

Design Engineer

India, Bengaluru, Karnataka
... Hands on experience on high speed interfaces, Micro architecture Design, Synthesiss friendly RTL Development. SUMMARY: 4+ years of experience in design, development, and debugging of various applications like Broadcasting Encoders, AES based Digital ... - Jul 07

Firmware Engineer with 5+ years of experience working with fpga, cpld

United States
... Tasks include: VHDL RTL design of a microcontroller (Motorola 68302), COM20020 chip, sram and flash interface, CPLD and FPGA device selection and pinout, synthesis, layout, RTL/Gate level simulation and debugging, and timing analysis. Tools used ... - Jul 02

Software Developer Engineer

Los Angeles, CA
... Integrated the emulation build automation into validation environment to improve RTL quality. • Designed and supported C++ MPEG2 and scalable video coding (SVC) media decoders • Designed Perl client-server app for in-house use to improve continuous ... - Jun 30
1 2 3 4 5 6 7 Next