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VerilogHDL,Perl,TCL,Cadence virtuoso,spectre,RTL compiler,SoC encounte

India, Bengaluru, KA
... SKILLS Programming skills - Verilog HDL, C, Perl, TCL Professional tools - Cadence Spectre, Virtuoso, RTL Compiler, SoC encounter, Simvision, Modelsim, Quartus ACADEMIC Design of 45nm low power, High Speed, 64 bit Vedic Multiplier - PROJECTS Tools ... - Oct 28

FPGA design, Verilog, ASIC design, Altera Quartus II

India, Mumbai, MH
... TECHNICAL SKILLS Hands On Experience Software Tools Programming Languages Cadence – NC Launch, RTL Complier C, C++ Cadence – SoC Encounter (Back-end) Verilog Mentor Graphic- Model-Sim PERL Altera Quartus – II TCL Cadence – Virtuoso W orked on – 45nm ... - Oct 27

Engineering Design

India
... • CADENCE Encounter RTL Compiler. • Verilog/ VHDL/ System Verilog • MATLAB, Scripting • Synopsys: Design Compiler, Tetramax • C, C++ • MPLAB • PARI, HFSS • Multisim • Latex • 8085, PIC Assembly Programming • Keil • LABView PUBLICATIONS 1. Ramesh ... - Oct 26

System Verilog, Veriog, Functional Coverage

India, Robertson Pet, KA
... AREAS OF INTEREST ASIC Verification, RTL Design, SOC SEMINAR Verification Process Differential Amplifier In Sub-Threshold region BEYOND CURRICULUM AND ACHIEVEMENTS Secured Runners-up position in Inter Collegiate Volleyball Tournament in Feb 13 -14. ... - Oct 24

Systemverilog, basic UVM, verilog

Thailand
... Key contributions: Synthesized, verified the RTL design, and evaluated the functionalities and performance of a P2S module of the system to assist the communication between the processors, using Tcl scripts, Synopsys and Cadence Encounter ... - Oct 22

Project Engineer

India, Bengaluru, KA
... > Basic Knowledge in RTL Designing,Testing and Testability. > EDA Tools - Cadence Virtuoso,Glade,Keil-Microvision. EXTRA CURRICULAR ACTIVITIES: > Play cricket, chess, caromboard. > Listen to online Technical Videos(NPTEL). PERSONAL PROFILE : Date of ... - Oct 21

construction mangement( tile and marble srtter ) my trad

Santa Clarita, CA
... plor itlc tlltlcs ol'ctuPlor ttte rtl. lrre lrtiort. rrrttl rclrrrrtt lirt' scplrntlitllt Irrrrtt crttplor rttcnt. NtiXf I o INs'l l(tr(.'1'IONS I'ol{ ANSWI:RIN(;-l'lilr QUI:S l'l NS l lcsrtltctl irr rcll'rt'lrl to tlir clsion PI(uruln. ;tPPlictrnts ... - Oct 20

Design Training

India, Kannur, KL
... [pic][pic] Freshman Email: acgfnp@r.postjobfree.com +919809801492 SKILL SET > C > EMBEDDED C > VLSI > DIGITAL DESIGN > VHDL/VERILG > MATLAB > ORCADD > XILINX ISE > CHIPSCOPE PRO > ALTERA > RTL DESIGN > EDA > MODEL SIM > FPGA OBJECTIVES To pursue a ... - Oct 20

Project Engineering

India, Chennai, TN
... • Good knowledge of Verilog RTL coding. • Good knowledge of Digital Design Concepts. • Good knowledge of Analog Design. • Education Examination University/School Year Class Obtained Percentage M.Tech in VLSI R.V. College of Pursuing First class 67% ... - Oct 19

Engineer Quality Assurance

Chicago, IL
... Specifications of Electronic Equipment, Technical Report Writing, Testing Theoretical Design Aspects, Using Measuring Equipment, Communicating on Technical Level with Other Engineers, RTL Design, Calculus and Mathematical Modeling Accomplishments 1. ... - Oct 18

Design Engineering

India
... • Experience in writing RTL models in Verilog HDL and familiar with System Verilog and UVM. • Knowledge of Digital electronics and CMOS fundamentals. ACADEMIC QUALIFICATIONS: DEGREE/ EXAMINATION UNIVERSITY/BOARD YEAR OF PASSING MARKS B. Tech ... - Oct 18

Project Engineering

India
... +91 973******* Summary of Qualifications > Good understanding of the ASIC and FPGA design flow > Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM > Very good knowledge in verification methodologies > ... - Oct 17

Design Engineer

India
... OVERVIEW Good understanding in Digital logic design & Electronics fundamentals • Good understanding of the ASIC/FPGA design flow • Experience in Verilog HDL to write synthesizable RTL, self-checking test benches& • Test benches in system Verilog ... - Oct 16

Good Knowledge in System Verilog, Verilog & UVM.

India, Bengaluru, KA
... Projects: Router 1x3 -- RTL design and Verification Team Size: 2 Role: Designed the model and verify its application. Responsibility: • Architected the design and described the functionality using Verilog HDL. • Architected the class based ... - Oct 16

Engineer Project

India, Hyderabad, Telangana
... July 2012 to September 2012 Role : UPF checks on large RTL and NETLIST designs. Environment : Linux(redhat) Tool : Monet (synopsys) Tool : Spyglass,DC Compiler Projects Undertaken at MCIS Manipal 1) TSPC LATCHES AND FLIPFLOPS CHARACTERIZATION ... - Oct 16

Vlsi Rtl Design And Testbench

India, Agra, UP
... Project4 : Clock Gated Low Power Sequential Circuit Design Description: In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. ... - Oct 14

Engineering Service

India, Bengaluru, KA
... > Working skills on RTL design and Static Timing Analysis . > Knowledge on FPGA, ASIC and Microprocessors. > Good at CMOS technology and Analog circuits. Projects > Implementation of CANNY EDGE DETECTION IN FPGA. Tools used : MATLAB R2013a : XLINIX ... - Oct 13

Vlsi Design,Verilog,System Verilog, I2c, Vip, Eda, Modelsim, Gvim,Rtl

India, TN
GOKULAKRISHNAN.S Email Id : acgck0@r.postjobfree.com */179,singarapettai st., Thirumani, Contact : +91 848******* Thiruvannamalai - 604504. CAREER OBJECTIVE: Aspiring for a career that places me in a challenging position and learning-oriented... - Oct 12

Project Data

India, Hyderabad, Telangana
... Experience in RTL Design using VHDL,Verilog. Developed OVM Test bench environments for different modules. Experience in Functional Verification using constraint random and coverage driven methodology. Involvement in complete Functional verification ... - Oct 10

Hardware / software Engineer

Austin, TX
... Simulation-based verification of RTL design with special emphasis on IO interface. . Discovered bugs, characterized them, offer appropriated solutions, and regressed bugs. . Reviewed project specifications; generated test plans, test cases, and ... - Oct 09
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