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Project Engineer

India map
... Programming Languages: Verilog (HDL's), M.Des PROJECT: Title : FIR Filter architecture for SDR My Role : Developed the RTL code for Multiplier, Adder and test bench Language : Verilog Description : Developing an optimum design to decrease the ... - May 22

Design Technical

India, Kozhikode, Kerala map
... to 2006 AISSE 68.60% S.V.N.C.S,Kodakara Technical skills Programming Languages VHDL, Verilog HDL,C and PERL EDA Tools Cadence RTL Compiler, SoC Encounter, Xilinx-ISE, NCSim Hardware Virtex-2pro, Sparten-3E FPGA boards Academic Projects M-Tech 1. ... - May 21

Project Security

India, Noida, Uttar Pradesh map
... Wrote algorithms in Verilog HDL at RTL for Architecture. Verified with several test benches and synthesized in Xilinx ISE The design has been implemented on a range of FPGAs to compare the performance . Common-Gate Low-Noise Amplifier (LNA) A fully ... - May 20

Project Design

India, Ambavaram, Andhra Pradesh map
... Listening to music Areas of interest : RTL Coding, FSM based Arts design, Simulation, Design of VLSI technology, Physical design flow of ASIC And Testing. Strengths . Ability to work in a group excellently. . Optimistic and persistent even under ... - May 20

Administrative Assistant Data Entry

St. Peters, MO map
... Received and processed purchase orders into automated tracking system using RTL and Sales Logix Software and ensured orders are processed and properly recorded based upon account, product and payment . Input various forms of data into systems and ... - May 19

Project Design Engineer

India map
... Responsibilities : > Designing and Implementing synthesizable RTL code. > Integrating all the RTL modules for acquisition process. > Writing test bench to verify design functionality and Timing. > Validating the design on the hardware. Project 2 : ... - May 18

FPGA /Hardware / Design/ Validation/ Verification/ electrica Engineer

Coppell, TX map
... GPA 3.8 June 11 Professional Experience: DRD/SII Hardware Intern Jan 14 – Sep 14 Intel Corporation, Hillsboro OR • Primarily Supported the Pre-Si Platform Integration Team in RTL Simulation, Software Driver Enabling/Validation, IP Development, ... - May 18

Design Engineer

India map
... Team Size :4 AREAS OF INTEREST ASIC Design RTL Design of Systems Physical Design Memories TECHNICAL SKILLS Programming Languages C, C++, HTML, MATLAB & Simulink Verilog HDL (using Xilinx ISE Editor for FPGA, Cadence NClaunch for ASIC), Embedded-C ... - May 18

Planner

Philippines, Bacoor City, CALABARZON map
... cleaning, etc.), Interior refurbishment, etc.) Aircraft delivery and acceptance (NEW and USED aircraft): from OEM / Return-To-Lessor (RTL) / In-Lease Acceptance (ILA) / overseeing End-Of-Lease (EOL) check / Lease agreement evaluation Aircraft of ... - May 18

c,Data Structures, System Verilog,Vlsi design

India, Ernakulam, Kerala map
... EDA Tool : Cadence Virtuoso, RTL Compiler, NCSIM . Operating systems: Linux,Windows Xp/7/8 . Languages : C, System Verilog, Verilog, HDL Extra curricular 1. Attended "ETHICAL HACKING" program conducted by IEEE which was held at MCE Hassan. 2. ... - May 18
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