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Industrial Automation,PLC Embedded system, Analog & Digital design etc

India map
... THESIS “Ultra Low Temperature Performance Modeling For 180nm MOSFET Technology” EXPERIENCE Good knowledge in analog & digital design circuits in tools like CADENCE VIRTUOSO, Ng- Spice, Cool-Spice and P-Spice Knowledge of Digital circuit design, RTL ... - Sep 03

Digital Design Engineer

Chandler, AZ map
... Smiley Chandler, AZ ● 623.***.**** ● acrij5@r.postjobfree.com Dedicated and accomplished Digital Design Engineering Professional offering 28 years of expertise in SoC architecture, RTL design and debugging. Capable leader with the ability to manage ... - Sep 02

Test Cases Design

India, Bengaluru, Karnataka map
... Keen interest in the areas of Digital VLSI Design & Verification, System Design, RTL Design and Semiconductor Devices (Simulation & Modelling) An effective communicator with strong analytical, problem solving & interpersonal skills Education 1. B.E. ... - Sep 01

Engineer Years Experience

Santa Rosa, CA map
... including graphic Zed Graph 3+ years experience software development using C++, Java in-depth knowledge of popular protocols UART, SPI, I2C, TCP/IP with both low-level SW implementation and chip-level FPGA implementation 18+ years experience in RTL ... - Aug 27

Digital Design, VLSI, Static Timing Analyses, Scripting, Layout, IC.

India map
... Six weeks training in RTL Design at DKOP Labs, Noida. PROJECTS: Title : CAM based packet switched network Platform : RTL Coding (Verilog/SystemVerilog/VHDL) Description : This project focuses on implementing a simplex packet switched network that ... - Aug 24

Digital Design, Digital signal processing, Verilog Programming

India, Hyderabad, Telangana map
... College, Jangaon BIE, Andhra Pradesh 2008 95.60 I SSC APSWR School, Ghanpur Station BSE, Andhra Pradesh 2006 83.67 I COMPUTER PROFICIENCY: Programming: RTL Verilog, MATLAB script, C Tools: MAT LAB, Xilinx ISE, Aldec Riviera, Model Sim, Vivado. ... - Aug 23

Project Engineer

India map
... One day Hands-on Training Programming on VLSI system design (RTL-GDSII) using CADENCE at University of Madras. Proficiency at grasping new technical concepts quickly & utilizing it in a productive manner. BASIC ACADEMIC CREDENTIALS B.Tech ... - Aug 23

Verilog, System verilog, UVM

India, Bengaluru, Karnataka map
... Summary of Qualifications Good understanding of the ASIC design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM Experience in using industry standard EDA tools for the front-end design and verification ... - Aug 23

Fresher_M.tech in VLSI design and Embedded systems

India, Bengaluru, Karnataka map
... Good understanding of fundamentals of Transistors and circuit theory Good knowledge of Verilog RTL coding Good knowledge of Digitial Design Concepts Good knowledge in MATLAB and VHDL coding. Excellent knowledge of IC Fabrication process Good working ... - Aug 22

Electrical Engineer Microsoft Office

Long Beach, CA map
... Synthesized and created the circuit of a full adder using Verilog/VHDL software, developing a Xilinx code that generated RTL (resister transfer level) schematic and test bench results. (b) Designed a CMOS Inverter using Microwind . Designed a CMOS ... - Aug 21
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