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M.Tech in VLSI

India, Hyderabad, Telangana map
... Experience in writing RTL models in Verilog HDL, VHDL and Test benches in SystemVerilog. Experience in using industry standard EDA tools for the front-end design and verification. Developed RTL codes for M.Tech academic and research VLSI projects. ... - Feb 27

Engineer Design

Lake Forest, CA map
... RTL coding with Verilog, VHDL. 2. System-On-Chip design on both Xilinx and Altera FPGA. 3. Knowledge of SOCs with embedded CPUs, DMA, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCIE, Serdes SPI, UART, I2C, etc 4. Embedded ... - Feb 25

Manager Assistant

Europe map
... Budapest RTL KLUB- Assistant editor and decorator 2009: Sikl s Municipality- Mayor's Secretary 1998-2008: Florist Sikl s- Florist and Manager MAIN TASKS: Executive Secratary: -Director of the daily program schedule -Skilled interviewing -Purchase of ... - Feb 25

Design Engineer

India, Bengaluru, Karnataka map
... Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog and UVM. Experience in using industry standard EDA tools for front-end design and verification. Experience in System Verilog, UVM methodology and Perl. 1.5 experience ... - Feb 24

Engineer Project

India, Bengaluru, Karnataka map
... Good understanding of the ASIC/FPGA front-end Design and Verification Extensive experience in writing RTL models in Verilog HDL and Testbenches in SUMMARY OF SystemVerilog and UVM QUALIFICATIONS Experience in using industry standard EDA tools for ... - Feb 19

Design Project

India, Bengaluru, Karnataka map
... RTL Verification. Embedded controller based product design. TECHNICAL SKILLS EDA TOOLS ModelSim, Xilinx ISE design suite, Quartus II, OR-CAD Layout plus. Keil-μvision, Cadence-NC Launch. OPERATING SYSTEM Windows XP, 7 & 8. LANGUAGE Basics of C & C++ ... - Feb 19

Project Design

India, Bengaluru, Karnataka map
... Cadence UMC .18um (Virtuoso/Virtuoso Writing RTL code. XL tool), Mentor Graphics and Tanner. Verilog, VHDL, SystemVerilog Schematic and Layout designing, DRC, (Xilinx, QuestaSim). LVS, Post layout (Parasitic PERL as Scripting Language. extraction) ... - Feb 18


India, Bengaluru, Karnataka map
... Core Competency: Good understanding of fundamentals of Transistors and circuit theory Good knowledge of Verilog RTL coding Good knowledge of Digital Design Concepts Good exposure to technology by undergoing additional training in VLSI Implemented a ... - Feb 18

Design Engineer

India, Hyderabad, Telangana map
... Responsibilities : RTL coding for the JTAG interface of the Controller using FSM Tools : Modelsim /Questasim, VCS Language : Verilog IP Development for MIL STD 1553B Description : This protocol is widely used in Defence Avionics and Submarines for ... - Feb 17

Design Engineer

Santa Clara, CA map
... Work Experience: Scalable Systems Research Labs, Inc August 2014 – Present Design Engineer (Verilog RTL Design) Responsibilities • Design of Floating point multiply unit for 64-bit multiplication using Fused Booth Encoder Multiplexer. • Implement a ... - Feb 16
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