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Project Manager Data

Bellevue, WA
... Designed and collaborated with dev on developing the automation tools to enable the auto-alignment for the RTL languages. Previous Experience International Project Manager (Microsoft Interactive Training Division, Redmond, WA.) Localization Project ... - May 26

Engineer Test Cases

India
... Verilog, SystemVerilog, VHDL, SystemVerilog Assertions, UVM ASIC/FPGA Design Flow, Digital Design methodologies, test and checker plan development RTL Coding, FSM based design, Simulation, Synthesis Perforce & Code Collaborator Code Coverage, ... - May 25

Data Project

India, Bengaluru, Karnataka
... Technical Skills Programming Languages: Verilog,System Verilog Verification Methodologies: System Verilog, UVM Protocols: UART EDA Tools: Xilinx, Riviera-Pro, Mentor Graphics-Questasim Domain Knowledge: ASIC/FPGA front-end Design, Verifying RTL ... - May 24

Electrical Engineering Engineer

Mays Landing, NJ
... • Skills : ASIC Design, RTL coding, Synthesis, Floorplanning, APR, Static timing analysis (STA), Digital Circuit Design, CMOS and VLSI Design, Low power analysis, Scripting(perl), Computer Architecture and Design-for-Test (DFT) EDUCATION: Master of ... - May 23

Design Engineering

India, Bengaluru, Karnataka
... Engineering College,Anna University, Chennai Good understanding of ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Testbenches in System Verilog and UVM Very good knowledge in verification methodologies ... - May 23

Design Engineering

India, Bengaluru, Karnataka
... Engineering College,Anna University, Chennai Good understanding of ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Testbenches in System Verilog and UVM Very good knowledge in verification methodologies ... - May 23

Project Design

India, Bengaluru, Karnataka
... : FPGA •Expertized in : Understanding of VLSI & ASIC design flow FPGA architecture Logic and Circuit design Synthesis and timing analysis RTL Verification IP/chip level verification TRAININGS •PG Certification in VLSI Design from DKOP Labs Pvt. ... - May 23

Project Engineer

India, Bengaluru, Karnataka
... Polytechnic 2011 SSC Z.P.H.School Vuyyuru 2008 Projects Implemented RTL Design and Implementation of RISC Processor– This Project is aimed to designing of a Reduced Instruction Set Computer (RISC) Processor SoC for low power Embedded and Mobile ... - May 23

Project Engineer

India, Bengaluru, Karnataka
... Currently working as a RTL Design and Verification Engineer at Aeronautical Development Agency (ADA), Ministry of Defence, and Govt. of India on deputation from M/s Sheeba Computers & business solutions international, Bangalore since from Dec 2013 ... - May 19

Hardware Design Engineer

Dallas, TX
... Seeking for fall’16 internship in VLSI/ASIC Physical design-RTL to GDS EDA design, RFIC Design, Architecture design, Advanced digital logic design, Verification and Validation to utilize my skill set in Digital circuit design from May to Dec 2016. ... - May 18
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