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Training Java

India, New Delhi, Delhi map
... SKILLS AND ABILITIES Knowledge Knowledge about Orcad(PSPICE), Tanner EDA,, Proteus,, avr studio, Xillinx,turbo c C Language C++ Language JAVA programming language using Java SE6. Training 2 day Technical workshop on Trends in CMOS based Analog ... - May 27

Design Electrical Engineer

United States map
... Systems Engineering VLSI Design Advanced Digital Logic Testing and Testable Design Semiconductor Processing Technology Technical Skills and software: Tools: EDA Cadence Virtuoso, Hspice, EDI Encounter in Cadence, CPP Sim Viewer, GEDA, ngspice, UVM. ... - May 26

Electrical Engineer Mechanical

Milpitas, CA map
... • Generate ECO (Engineering Change Order), ECR (Engineering Change R equest), EDA (Engineering Deviation Authorization) going th rough P roduction/Document Control process. • I n tegrate and implement the systems with the document verification. • ... - May 26

vlsi design and verification engineer

India, Mumbai, Maharashtra map
... Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology: UVM Protocols: UART(ongoing) EDA Tool: Questasim and ISE Domain: ASIC/FPGA front-end Design and Verification Knowledge: RTL Coding, FSM based design, ... - May 26

Electrical Engineering Design

Riverside, CA map
... Narsee Monjee Institute of Management Studies (NMIMS) University, Mumbai, India GPA: - 3.2/4.00 June 2014 TECHNICAL SKILLS EDA Tools: Cadence Virtuoso, Cadence Encounter v7.1, Syncad Verilogger, Tina PRO, Kiel Microwind Programming: C, C++, ... - May 25

Design Engineer

India map
... > Tools: Cadence OrCAD Schematic and PCB Design tools, Xilinx ISE Design9.1, VCS, Cadence EDA Tools (IUS & RTL Compiler). ACADEMIC PROJECTS CVC Projects: 1. Design and Verification of AMBA-APB Interface Protocol. Tools Used: Mpsim and Xilinx ISE. ... - May 25

Engineer Engineering

India, Bengaluru, Karnataka map
... o EDA Tools : Mat lab, Xilinx (Basics), PLC. o Packages : MS Office, MS Dos. ACHIEVEMENTS: o I am one among the toppers in my academics. o Won 3rd prize in the Cricket held in our college. o I had won second prize in 'TECHNICAL QUIZ' conducted by ... - May 25

Looking for Internship- M.Tech VLSI- ASIC/FPGA

India map
... EDA Tools: Cadence, Mentor Graphics Languages: VHDL, Verilog, C TRAININGS AND CERTIFICATIONS: • GATE 2014 qualified, with a score of 436. • Undertaking an online course on ‘SOC Verification using System Verilog’ by Udemy. • Implant training on ... - May 25

Engineer Training

India, Mumbai, Maharashtra map
... Skill Set EDA Tools : Microwind, Dsch,Xilinx,Modelsim Hardware Description Languages : Vhdl, Verilog, System Verilog. Software Skills : C,C++ and embedded C Platforms : Windows, unix Hardware Expertise : CPLD, FPGA Board (Spartan 3) DT Survey Tools ... - May 25

Fresher with 71.6 % in B.Tech with a major in ECE,2015 passout.

India map
... • EDA Tools: Xilinx ISE 14.7 • Simulation Tools: P Spice, ModelSim,MATLAB • Assembly Languages: Intel 8051, 8085, 8086, PIC Microcontroller • Made mini projects on ATMEGA8 (ardiuno) like line follower CO /EXTRA –CURRICULAR ACTIVITIE • Core Member of ... - May 24
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