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Get new resumes like this by email Resumes 1 - 10 of 1997

Electrical Engineer Design

Santa Clara, CA
... SKILLS Programming Languages : C, C++, Perl Hardware Languages : Verilog, VHDL, MATLAB Operating Systems : Windows, Linux EDA Tools : Cadence Virtuoso, Encounter, Design Vision, Prime Time, Xilinx ISE14.1, HSpice, Virtual Photonics, NI AWR Design ... - Aug 30

RTL to GDS II, Verilog, System Verilog, TCL, Perl, C

Austin, TX
... C and Matlab TCL, Perl, Csh Scripting Experience on Unix/Linux Work under minimal supervision Strong problem solving skills EDA Tools: Simulators NCSim Questa Synapticad Cadence Virtuoso Spectre Encounter Tempus RTLCompiler Voltus Synopsys Primetime ... - Aug 29

Electronics, semiconuctors, MS office

Thousand Oaks, CA
... ß Tools: Microsoft office, PSPICE, T-spice, Cadence Virtuoso, EDA and Basics of Altium Designer. Academic Projects: Design, development and implementation of 32-bit pipelined CPU with high speed architecture The CPU design was implemented with a ... - Aug 26

Technical Support Quality Assurance

Santa Clara, CA
... acceptance Test Cases for all products from requirements Developed Factory Automation scripts for laser, stepper, metrology and EDA products Provided and/or reviewed root cause analysis to optimize test plans for overall quality improvement Created ... - Aug 26

System High School

India
... Area of Interest RTL Design and Verification Digital VLSI Design EDA Tool designing personal Traits 1.Innovative Thinker 2.Goal Focused 3.Quick Learner 4.Leadership quality References Neeraj Kr. Shukla Professor Department of EECE ITM University ... - Aug 23

VlSI design

Dallas, TX
... Experienced with high level programming languages C, JAVA, EDA tools and design verification with UVM. Ability to read and understand schematic designs and excellent verbal and written skills to interact with design teams. EDUCATION Master of ... - Aug 22

Manufacture and protection

India, Coimbatore, Tamil Nadu
... In this project the important parameters for VLSI applications like delay, area and powerconsumption are taken into account and verified in 180nm technology carry look adder and carry skip adder using Cadence EDA tool. The reults are compared and ... - Aug 19

Manager Design

India
... TECHNICAL SKILLS Software Skill : C HDL : Verilog Platform Worked-on : Windows xp/Vista/7/8, Linux EDA Tools : Xilinx ISE design suite, Model-Sim, Questa-Sim, NC-Sim EDUCATION Qualification Year Institution University/Board Percentage/ CGPA M. Tech. ... - Aug 18

Sales Representative Office

Philippines, Legazpi City, Bicol
Eda A. Hernandez April **, **** F. Imperial St. Legazpi City Legazpi City, Albay Philippines 4500 +639095044475 acv442@r.postjobfree.com OBJECTIVE I am seeking a competitive and challenging workplace where I can serve your organization and establish ... - Aug 12

Verification Engineer

India, Bengaluru, Karnataka
SRINIVAS Mobile : +**-953******* Email: acv4ff@r.postjobfree.com Professinal Summary Having around 2 years of professional experience in Semiconductor Industry, Involved in ASIC Verification projects and EDA Tools like Questa sim,Quartus and Mode ... - Aug 11
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