| Resume alert | Resumes 31 - 40 of 2013 |
C++ Software Developer
Dover, MA, 02030
... I also had to debug issues found in the user designs (Soc, Asic, Fpga) written in RTL/GA by using SystemVerilog, SV assertions, Vpi/Pli/Cli/Dki, coverage. The changes helped the company to secure better contracts with customers like Apple, Intel, ... - Jan 29
... I also had to debug issues found in the user designs (Soc, Asic, Fpga) written in RTL/GA by using SystemVerilog, SV assertions, Vpi/Pli/Cli/Dki, coverage. The changes helped the company to secure better contracts with customers like Apple, Intel, ... - Jan 29
B C 1 0
Indianapolis, IN
... 'V 踦 /dK TI U 2o Z2t )P+o e Z Ɋ P ͭ F Ȕ sEZ ece _ A +̏ 9 1 b w G, MXV LE k cs 7@c y ) 3x 2 c q y m u TW\F h1 ̕ 2 ݯ D a K Dlj Rtl In M us jaJ G B S W yB ~nb 1 P Xc *ŨO \P R H ֔1 :H ̫X] H ޅ W 07 v'-Y ʟN !w2 vO 聋 D P RuS q P2 &D Ṕ巷 J _ бo C ӳ Ꜳ sW p o ... - Jan 25
... 'V 踦 /dK TI U 2o Z2t )P+o e Z Ɋ P ͭ F Ȕ sEZ ece _ A +̏ 9 1 b w G, MXV LE k cs 7@c y ) 3x 2 c q y m u TW\F h1 ̕ 2 ݯ D a K Dlj Rtl In M us jaJ G B S W yB ~nb 1 P Xc *ŨO \P R H ֔1 :H ̫X] H ޅ W 07 v'-Y ʟN !w2 vO 聋 D P RuS q P2 &D Ṕ巷 J _ бo C ӳ Ꜳ sW p o ... - Jan 25
Consumer Products Embedded Software
Los Gatos, CA
... 2002 – 2008 Verification Architect Nvidia Santa Clara CA Led 17 software engineers developing C model and Verilog RTL verification infrastructure of 50+ million gate graphics integrated circuits. Supported teams at multiple sites in U.S. and India. ... - Jan 19
... 2002 – 2008 Verification Architect Nvidia Santa Clara CA Led 17 software engineers developing C model and Verilog RTL verification infrastructure of 50+ million gate graphics integrated circuits. Supported teams at multiple sites in U.S. and India. ... - Jan 19
Electrical Engineering Verification Engineer
Long Beach, CA
... CERTIFICATIONS: PHYSICAL DESIGN ENGINEER TRAINING Course via VLSIGuru (06/2023 – 12/2023) • Hands-on experience in fundamental concepts and advanced techniques in digital design and implementation, including synthesis, RTL analysis, timing ... - Jan 18
... CERTIFICATIONS: PHYSICAL DESIGN ENGINEER TRAINING Course via VLSIGuru (06/2023 – 12/2023) • Hands-on experience in fundamental concepts and advanced techniques in digital design and implementation, including synthesis, RTL analysis, timing ... - Jan 18
1 0 Cleaning Technician
Kearns, UT, 84118
... } [dir="rtl"] #upsellBannerForPad iframe, [dir="rtl"] #upsellBannerForPhone iframe { padding: 0px 28px 20px; } #upsellBannerForPad button, #upsellBannerForPhone button { min-width: 1px; height: 32px; margin: 0px; padding: 0px; color: rgb(0, 0, 0); ... - Jan 18
... } [dir="rtl"] #upsellBannerForPad iframe, [dir="rtl"] #upsellBannerForPhone iframe { padding: 0px 28px 20px; } #upsellBannerForPad button, #upsellBannerForPhone button { min-width: 1px; height: 32px; margin: 0px; padding: 0px; color: rgb(0, 0, 0); ... - Jan 18
Team Lead Product Designer
Lake Arrowhead, CA
... ● Led the design effort on localizing our app internationally accommodating 4 languages including Arabic RTL support. ● Led design effort in creating an atomic based design system and gaining buy-in from stakeholders to achieve engineering parody. ... - Jan 17
... ● Led the design effort on localizing our app internationally accommodating 4 languages including Arabic RTL support. ● Led design effort in creating an atomic based design system and gaining buy-in from stakeholders to achieve engineering parody. ... - Jan 17
Electronics Engineer: Fpga/Asic/Soc/Pcb/Mcu/Cpu
Greensboro, NC
Nidhi Gupta FPGA Engineer Scrum Master ad2unl@r.postjobfree.com, +1-336-***-**** LinkedIn Profile: https://www.linkedin.com/in/masters-electronics-guptanidhi/ Current Focus: IP based complex designs, RTL, Simulation, Testbench, Timing Closure ... - Jan 17
Nidhi Gupta FPGA Engineer Scrum Master ad2unl@r.postjobfree.com, +1-336-***-**** LinkedIn Profile: https://www.linkedin.com/in/masters-electronics-guptanidhi/ Current Focus: IP based complex designs, RTL, Simulation, Testbench, Timing Closure ... - Jan 17
Research Intern
New Brunswick, NJ
... E-Infochips-An ARROW Company June 2022 – July 2022 Intern Remote • Used the software OpenROAD to convert RTL (Resistor Tranfer Logic) designs into GDS-II (Graphic Data Stream) format, which is used for chip fabrication. • OpenROAD is an open-source ... - Jan 15
... E-Infochips-An ARROW Company June 2022 – July 2022 Intern Remote • Used the software OpenROAD to convert RTL (Resistor Tranfer Logic) designs into GDS-II (Graphic Data Stream) format, which is used for chip fabrication. • OpenROAD is an open-source ... - Jan 15
FPGA and Asic Design Engineer
Oceanside, CA
... Expert in high speed, high density FPGA design and development, SoC and ASIC design, simulation, verification, RTL development and synthesis, Xilinx (AMD) and Altera (Intel) FPGA tools, platforms and technologies. Experience with ZYNQ UltraScale+ ... - Jan 12
... Expert in high speed, high density FPGA design and development, SoC and ASIC design, simulation, verification, RTL development and synthesis, Xilinx (AMD) and Altera (Intel) FPGA tools, platforms and technologies. Experience with ZYNQ UltraScale+ ... - Jan 12
Java Developer C C++
Alpharetta, GA
... • Micro Architecture Development and RTL designed in Verilog. • Designed on Vertex 6 FPGA board using Chip scope analyzer tool. • Involved in device driver development for PCI express. Tools Used: Xilinx ISE, MATLAB and Chip scope analyzer. Language ... - Jan 11
... • Micro Architecture Development and RTL designed in Verilog. • Designed on Vertex 6 FPGA board using Chip scope analyzer tool. • Involved in device driver development for PCI express. Tools Used: Xilinx ISE, MATLAB and Chip scope analyzer. Language ... - Jan 11