| Resume alert | Resumes 91 - 100 of 2015 |
Control Systems Fpga Design
Visakhapatnam, Andhra Pradesh, India
... Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx Vivado Projects (using Verilog and implemented in FPGA) 4 ... - 2023 Sep 11
... Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx Vivado Projects (using Verilog and implemented in FPGA) 4 ... - 2023 Sep 11
Design Engineer Asic
Garden Grove, CA
... SKILLS Ability to quickly pick up new concepts and contribute with innovative solutions Strong Digital Logic Design background with ability to do RTL Design in VHDL and Verilog Verilog, VHDL synthesis System Modeling and Simulation testing ... - 2023 Sep 03
... SKILLS Ability to quickly pick up new concepts and contribute with innovative solutions Strong Digital Logic Design background with ability to do RTL Design in VHDL and Verilog Verilog, VHDL synthesis System Modeling and Simulation testing ... - 2023 Sep 03
Senior QA Automation Engineer Selenium C#
Plano, TX, 75074
... ● Functional Testing and Localization testing of CRM applications in 44 languages (includes RTL also). ● Testing new features in various configurations of OS and MS office which includes MAC Mini and MS Outlook. ● MS Dynamics CRM Mobile application ... - 2023 Aug 24
... ● Functional Testing and Localization testing of CRM applications in 44 languages (includes RTL also). ● Testing new features in various configurations of OS and MS office which includes MAC Mini and MS Outlook. ● MS Dynamics CRM Mobile application ... - 2023 Aug 24
Remote Software Intern
Boston, MA
... SKILLS ●Java, JavaFX, Python, Typescript, React, CSS, C, C++, R, Assembly, MATLAB, and Verilog ●Software development, Agile Methodology ●Network Engineering ●RTL circuit/Basic FPGA programming - 2023 Aug 17
... SKILLS ●Java, JavaFX, Python, Typescript, React, CSS, C, C++, R, Assembly, MATLAB, and Verilog ●Software development, Agile Methodology ●Network Engineering ●RTL circuit/Basic FPGA programming - 2023 Aug 17
ASIC/SOC Architect/Lead
Livermore, CA
... Cell: 510-***-**** adyynp@r.postjobfree.com https://www.linkedin.com/in/mabbas72/ Summary of Exeprience: Technical Leadership: •Led tape-outs across multiple process nodes (5nm, 7nm, 10nm, 14nm, 16nm, and 20nm) overseeing designs from RTL to GDSII. ... - 2023 Aug 15
... Cell: 510-***-**** adyynp@r.postjobfree.com https://www.linkedin.com/in/mabbas72/ Summary of Exeprience: Technical Leadership: •Led tape-outs across multiple process nodes (5nm, 7nm, 10nm, 14nm, 16nm, and 20nm) overseeing designs from RTL to GDSII. ... - 2023 Aug 15
Associate Producer Assistant Director
Atlanta, GA
... FIELD ASSOCIATE PRODUCER Bling Dynasty- 3 Ball Ent/ Netflix SEGMENT PRODUCER RTL- Season 3/ Discovery + TALENT PRODUCER Iyanla Fix My Life- OWN- Pigeon FIELD ASSOCIATE PRODUCER Little Women: Atlanta Lifetime- Kinetic FIELD ASSOCIATE PRODUCER Miami ... - 2023 Aug 11
... FIELD ASSOCIATE PRODUCER Bling Dynasty- 3 Ball Ent/ Netflix SEGMENT PRODUCER RTL- Season 3/ Discovery + TALENT PRODUCER Iyanla Fix My Life- OWN- Pigeon FIELD ASSOCIATE PRODUCER Little Women: Atlanta Lifetime- Kinetic FIELD ASSOCIATE PRODUCER Miami ... - 2023 Aug 11
Software Engineer C++
East Stroudsburg, PA
... Borland, Scotts Valley, CA, March 1991 - March 1995 Senior Software Engineer Hired to write the Run-Time Library (RTL) for a planned FORTRAN compiler. ● Designed and implemented the I/O library support for the FORTRAN-77 and FORTRAN-90 feature sets. ... - 2023 Aug 08
... Borland, Scotts Valley, CA, March 1991 - March 1995 Senior Software Engineer Hired to write the Run-Time Library (RTL) for a planned FORTRAN compiler. ● Designed and implemented the I/O library support for the FORTRAN-77 and FORTRAN-90 feature sets. ... - 2023 Aug 08
Fpga Design Full Time
Irving, TX
... Employment History ASIC RTL/FPGA Design – Moneta Technology – April 2022 till January 2023 (Full Time) ●ASIC RTL Design - Simulations using Synopsys Verdi (VCS-FSDB). ASIC System Verilog RTL. ●FPGA RTL Design - ASIC emulation via Nomachine AWS CLI ... - 2023 Aug 06
... Employment History ASIC RTL/FPGA Design – Moneta Technology – April 2022 till January 2023 (Full Time) ●ASIC RTL Design - Simulations using Synopsys Verdi (VCS-FSDB). ASIC System Verilog RTL. ●FPGA RTL Design - ASIC emulation via Nomachine AWS CLI ... - 2023 Aug 06
Firmware Engineer Software Development
Austin, TX
... Testing used Cadence RTL compiler (xcelium) and debugger (simvision) running on Linux server. Tested Blake2b hashing algorithm functionality. Passed all benchmark tests. Investigated porting of Real Time Operating Systems (RTOS) to RISC-V: FreeRTOS, ... - 2023 Jul 20
... Testing used Cadence RTL compiler (xcelium) and debugger (simvision) running on Linux server. Tested Blake2b hashing algorithm functionality. Passed all benchmark tests. Investigated porting of Real Time Operating Systems (RTOS) to RISC-V: FreeRTOS, ... - 2023 Jul 20
Team Lead Rtl Design
Austin, TX
SRINIVAS KUMAR CH Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for ... - 2023 Jul 12
SRINIVAS KUMAR CH Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for ... - 2023 Jul 12