| Resume alert | Resumes 81 - 90 of 2018 |
Senior HW FPGA Engineer
United States
... Summary of Skills and Experience: • FPGA/ASIC Digital Logic Systems Design, Implementation, Emulation, and Optimization: RTL-level architecture and detailed level design, coding, and optimization using VHDL, System/Verilog, StateCAD, schematic, etc. ... - 2023 Nov 21
... Summary of Skills and Experience: • FPGA/ASIC Digital Logic Systems Design, Implementation, Emulation, and Optimization: RTL-level architecture and detailed level design, coding, and optimization using VHDL, System/Verilog, StateCAD, schematic, etc. ... - 2023 Nov 21
Front End Solution Architect
Charlotte, NC
... Front End Engineering Backend Engineering Cloud Engineering Site Reliability Engineering Program Management Primary Tech Stack: JavaScript TypeScript React & Hooks React Native Redux & RTK NodeJS GraphQL NextJS Angular Jest & RTL <Styled-Comp> ... - 2023 Nov 20
... Front End Engineering Backend Engineering Cloud Engineering Site Reliability Engineering Program Management Primary Tech Stack: JavaScript TypeScript React & Hooks React Native Redux & RTK NodeJS GraphQL NextJS Angular Jest & RTL <Styled-Comp> ... - 2023 Nov 20
Software Engineering Electrical
Fremont, CA
... Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure AI, ... - 2023 Nov 18
... Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure AI, ... - 2023 Nov 18
Verilog, Python, C/C++
Phoenix, AZ, 85003
... Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency ... - 2023 Nov 17
... Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency ... - 2023 Nov 17
Software Engineer Senior Manager
Highlands Ranch, CO
... 2002 - April 2005 • Support assemblers (VC++, STL) for generating hexadecimal byte code from firmware RTL for DSP chips. Worked with chip designers and firmware engineers. • Designed and developed an AutoConv tool to automatically upgrade firmware ... - 2023 Nov 15
... 2002 - April 2005 • Support assemblers (VC++, STL) for generating hexadecimal byte code from firmware RTL for DSP chips. Worked with chip designers and firmware engineers. • Designed and developed an AutoConv tool to automatically upgrade firmware ... - 2023 Nov 15
Operations Manager Shift Supervisor
Nadym, Yamalo-Nenets Autonomous Okrug, Russian Federation
... Act in the capacity of Armed Responder Response Team Leader (RTL), supervision of on-site response team in the event of an elevated threat level, site contingency or Active shooter event; Liaison between site security, plant operations manager and ... - 2023 Nov 10
... Act in the capacity of Armed Responder Response Team Leader (RTL), supervision of on-site response team in the event of an elevated threat level, site contingency or Active shooter event; Liaison between site security, plant operations manager and ... - 2023 Nov 10
Entry Level Fpga Design
New Delhi, Delhi, India
... AVR MCU Area of Interest: Digital Electronics RTL Design Analog Electronics Microelectronics Advanced Vlsi design EDUCATION B.Tech, Electronics & Communication Engineering 2012 Marathwada Institute of Technology-Bulandshahr, Uttar Pradesh, India M. ... - 2023 Nov 08
... AVR MCU Area of Interest: Digital Electronics RTL Design Analog Electronics Microelectronics Advanced Vlsi design EDUCATION B.Tech, Electronics & Communication Engineering 2012 Marathwada Institute of Technology-Bulandshahr, Uttar Pradesh, India M. ... - 2023 Nov 08
Land Surveyor Project Management
Qibla, 14, Kuwait
Work Experience: Qawader Al-Kwaitia Company Feb 2023 till now The role of land surveying is crucial in various projects, as it ensures accurate measurements and mapping of the earth’s surface. infrastructure work, finishing work, pipeline, stick out... - 2023 Nov 06
Work Experience: Qawader Al-Kwaitia Company Feb 2023 till now The role of land surveying is crucial in various projects, as it ensures accurate measurements and mapping of the earth’s surface. infrastructure work, finishing work, pipeline, stick out... - 2023 Nov 06
Design Engineer Rtl
San Jose, CA, 95118
... *** ****, CA ***** 408-***-**** ad0rh8@r.postjobfree.com ASIC/SOC VERIFICATION/DESIGN ENGINEER HIGHLIGHTS Have thorough understanding of different RTL design and verification strategies suited for today's applications. Architected Low Power ... - 2023 Oct 31
... *** ****, CA ***** 408-***-**** ad0rh8@r.postjobfree.com ASIC/SOC VERIFICATION/DESIGN ENGINEER HIGHLIGHTS Have thorough understanding of different RTL design and verification strategies suited for today's applications. Architected Low Power ... - 2023 Oct 31
Professional Mechanical Engineering Engineer
Quezon City, Philippines
... November 1, 2009 to June 30, 2011 Employer: Schweitzer-Mauduit International (SWM RTL) Philippines, Inc. Position: Project Engineering Manager PROJECTS UNDERTAKEN AND NATURE OF WORK: Manages the implementation of the Reconstituted Tobacco facility ... - 2023 Oct 15
... November 1, 2009 to June 30, 2011 Employer: Schweitzer-Mauduit International (SWM RTL) Philippines, Inc. Position: Project Engineering Manager PROJECTS UNDERTAKEN AND NATURE OF WORK: Manages the implementation of the Reconstituted Tobacco facility ... - 2023 Oct 15