| Resume alert | Resumes 101 - 110 of 2017 |
ASIC/SOC Architect/Lead
Livermore, CA
... Cell: 510-***-**** adyynp@r.postjobfree.com https://www.linkedin.com/in/mabbas72/ Summary of Exeprience: Technical Leadership: •Led tape-outs across multiple process nodes (5nm, 7nm, 10nm, 14nm, 16nm, and 20nm) overseeing designs from RTL to GDSII. ... - 2023 Aug 15
... Cell: 510-***-**** adyynp@r.postjobfree.com https://www.linkedin.com/in/mabbas72/ Summary of Exeprience: Technical Leadership: •Led tape-outs across multiple process nodes (5nm, 7nm, 10nm, 14nm, 16nm, and 20nm) overseeing designs from RTL to GDSII. ... - 2023 Aug 15
Associate Producer Assistant Director
Atlanta, GA
... FIELD ASSOCIATE PRODUCER Bling Dynasty- 3 Ball Ent/ Netflix SEGMENT PRODUCER RTL- Season 3/ Discovery + TALENT PRODUCER Iyanla Fix My Life- OWN- Pigeon FIELD ASSOCIATE PRODUCER Little Women: Atlanta Lifetime- Kinetic FIELD ASSOCIATE PRODUCER Miami ... - 2023 Aug 11
... FIELD ASSOCIATE PRODUCER Bling Dynasty- 3 Ball Ent/ Netflix SEGMENT PRODUCER RTL- Season 3/ Discovery + TALENT PRODUCER Iyanla Fix My Life- OWN- Pigeon FIELD ASSOCIATE PRODUCER Little Women: Atlanta Lifetime- Kinetic FIELD ASSOCIATE PRODUCER Miami ... - 2023 Aug 11
Software Engineer C++
East Stroudsburg, PA
... Borland, Scotts Valley, CA, March 1991 - March 1995 Senior Software Engineer Hired to write the Run-Time Library (RTL) for a planned FORTRAN compiler. ● Designed and implemented the I/O library support for the FORTRAN-77 and FORTRAN-90 feature sets. ... - 2023 Aug 08
... Borland, Scotts Valley, CA, March 1991 - March 1995 Senior Software Engineer Hired to write the Run-Time Library (RTL) for a planned FORTRAN compiler. ● Designed and implemented the I/O library support for the FORTRAN-77 and FORTRAN-90 feature sets. ... - 2023 Aug 08
Fpga Design Full Time
Irving, TX
... Employment History ASIC RTL/FPGA Design – Moneta Technology – April 2022 till January 2023 (Full Time) ●ASIC RTL Design - Simulations using Synopsys Verdi (VCS-FSDB). ASIC System Verilog RTL. ●FPGA RTL Design - ASIC emulation via Nomachine AWS CLI ... - 2023 Aug 06
... Employment History ASIC RTL/FPGA Design – Moneta Technology – April 2022 till January 2023 (Full Time) ●ASIC RTL Design - Simulations using Synopsys Verdi (VCS-FSDB). ASIC System Verilog RTL. ●FPGA RTL Design - ASIC emulation via Nomachine AWS CLI ... - 2023 Aug 06
Firmware Engineer Software Development
Austin, TX
... Testing used Cadence RTL compiler (xcelium) and debugger (simvision) running on Linux server. Tested Blake2b hashing algorithm functionality. Passed all benchmark tests. Investigated porting of Real Time Operating Systems (RTOS) to RISC-V: FreeRTOS, ... - 2023 Jul 20
... Testing used Cadence RTL compiler (xcelium) and debugger (simvision) running on Linux server. Tested Blake2b hashing algorithm functionality. Passed all benchmark tests. Investigated porting of Real Time Operating Systems (RTOS) to RISC-V: FreeRTOS, ... - 2023 Jul 20
Team Lead Rtl Design
Austin, TX
SRINIVAS KUMAR CH Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for ... - 2023 Jul 12
SRINIVAS KUMAR CH Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for ... - 2023 Jul 12
Electrical Engineer Design
Frisco, TX
... QUALIFICATIONS HIGHLIGHTS CPLD/FPGA _ VHDL/VERILOG HDL (RTL) High Speed Digital Design _ 10G Ethernet/Fibre Channel/Infini-band Telecommunications _ Optics, SONET/SDH/POS, ATM, TDM, IP Microprocessors/microcontrollers _ Motorola, Intel, embedded ... - 2023 Jul 10
... QUALIFICATIONS HIGHLIGHTS CPLD/FPGA _ VHDL/VERILOG HDL (RTL) High Speed Digital Design _ 10G Ethernet/Fibre Channel/Infini-band Telecommunications _ Optics, SONET/SDH/POS, ATM, TDM, IP Microprocessors/microcontrollers _ Motorola, Intel, embedded ... - 2023 Jul 10
Software Engineer
Chicago, IL
... English, Arabic · Localisation, RTL, LTR, ENVJson Language Parsing Skills Used, API Integration, Application Architecture MVC, Persistence, UI/UX. ● THELEVELe - Fashion & Beauty Online Shop: THELEVELe is the one-stop online mall for women across the ... - 2023 Jun 30
... English, Arabic · Localisation, RTL, LTR, ENVJson Language Parsing Skills Used, API Integration, Application Architecture MVC, Persistence, UI/UX. ● THELEVELe - Fashion & Beauty Online Shop: THELEVELe is the one-stop online mall for women across the ... - 2023 Jun 30
Electrical Engineer Robotics
La Puente, CA
... FPGA and CPLD RTL Logic Design and Simulation using Vivado, VHDL, Verilog. Digital-to-Analog and Analog-to-Digital Interface and Conditioning Circuits Design. Embedded Microprocessor/Microcontroller/DSP/DSC based applications Circuit Design and ... - 2023 Jun 19
... FPGA and CPLD RTL Logic Design and Simulation using Vivado, VHDL, Verilog. Digital-to-Analog and Analog-to-Digital Interface and Conditioning Circuits Design. Embedded Microprocessor/Microcontroller/DSP/DSC based applications Circuit Design and ... - 2023 Jun 19
Time Delivery Stack Developer
Ashburn, VA
... them using Grafana dashboard ●Improved Developer Experience (DX) by 15% by writing unit tests and integration tests respecting TDD with Jest and react-testing-library (RTL), which resulted in a 25% reduction in bugs and faster development cycles. ... - 2023 Jun 12
... them using Grafana dashboard ●Improved Developer Experience (DX) by 15% by writing unit tests and integration tests respecting TDD with Jest and react-testing-library (RTL), which resulted in a 25% reduction in bugs and faster development cycles. ... - 2023 Jun 12