To prove my worth by working in an organization where I can put my knowledge,
Skills, sincerity and dedication in making important contributions to the growth of the
• Languages : Verilog &VHDL, Basics of C & TCL
• : Cadence, MODEL SIM Simulator & Xilinx ISE
• Operating Systems : UNIX, Windows XP, Windows 2000.
• ERP : SAP R/3, VERSION: ECC 6.0 ABAP/4
Worked 0.6 Year in WIPRO TECHNOLOGIES as a PROJECT ENGINEER.
Completed THREE Months TRAINING in SYSTEM DESIGN domain.
In Training learned about timing calculations regarding signal integrity , Thermal
analysis ,Airflow Management in PCB design
Expertise in selecting the components like Resistors, Capacitors, Transistors, Oscillators,
Crystals, and Power Mosfets etc. required for PCB design.
Good Knowledge in selecting the alternate components for the components which are
Having Good Knowledge for preparing the Preliminary bill of materials and assembly
bill of materials which are used for ordering the components required for PCB design.
Learned about Clock Designing and Power Reset designing, and Interfacing between
different logic families like SSTL, HSTL, CML, LVPECL, PECL, ECL, LVDS etc. for
Learned about Interfacing between the Processor, memory and other peripherals.
Knowledge on EDA TOOL like CADENCE PCB DESIGN TOOL (ORCAD
ALLEGRO DESIGN ENTRY CIS) for symbol creation, drawing the schematics and
generating the final BOM (Bill of Materials) which is required for PCB layout design.
Learned to create the Net list From the Schematics which is required for PCB design.
Learned to check the Logical Symbol correctness Physical Symbol correctness power
and ground connection correctness in the Schematics.
Good knowledge on Board testing concepts .
Currently, I am doing course on ASIC front-end & back-end design.
Good Knowledge in Wave-form analysis, Verilog Coding & MODEL SIM Simulator.
Basic Knowledge on Physical Design and DFT.
Worked as a PROJECT ENGINEER in WIPRO TECHNOLOGIES from May 2011
to October 2011.
Project Name : PC Mother Board Design
Client : Wipro Technologies Internal Project
Company : Wipro Technologies
Platform : Cadence tool
Role : Project Engineer.
Wipro Technologies is a produce based company and it provide services like
IT and BPO. This project is based on the PC Mother Board Design using cadence tool. It
includes interfacing between processor memory and other peripherals like led, usb ports,
in this project I used DDR SDRAM processor from Micron, and flash memory, regulators,
Analyzing the client requirements and preparing functional block diagram according to
Selecting the components like ddr sdram, resistors, regulators, capacitors and eeproms
which are required for PCB design.
Preparing the Preliminary BOM which is required for ordering the long lead time
Creating the logical symbols for the components which are used for drawing the
schematics in cadence tool.
Interfacing the components as per the requirements using cadence tool.
Drawing the Schematics as per the requirement.
Generating Ne List from the Schematics using cadence tool.
Preparing the final BOM which is required for layout generation and also needed for PCB
Checking the connection correctness, logic symbol correctness, power and ground pin
connection correctness and pull up pull down decoupling capacitors correctness.
Field :Telecommunication-Bharat Sanchar Nigam Limited
Location : Hosur, Krishnagiri Dt.
Description :Indoor &Out door plant,Transmission,Cellular Technology,GenaralConcepts.
Final Year Project
Title: FLEXILICON: A RECONFIGURABLE ARCHITECTURE FOR DATA
• VLSI-VHDL Programming.
• This paper proposes a new reconfigurable architecture for data communications.
• The proposed architecture addresses three critical design issues with the loop level
parallelism, wide memory bandwidth, reconfigurable controller, and the support of
flexible word length.
• Several major functions of data communication applications were implemented in VHDL
to estimate the performance of the proposed architecture.
• Data Dictionary:
Tables, data elements ,structure, domain, views, search help, lock object.
Classical, Interactive and ALV Reports.
Internal table operations, Branching &Looping, Control break statement,
Join conditions, Select queries, .
• Module Pool Programming,
• BDC, SAP scripts, Smart Form, BAPI/BADI.
• Maintaining minimum 90% of attendance from 2006-2009 in college
• Received Merit Certificate in Volley Ball in school Level & 1500mts in college level.
• Received best project award in our college.
• I did my final year project in NLC(Neyveli Lignite Corporation Limited)- Neyveli.
• Actively attended workshop on “Embedded System” by ECE dept in Nehru Institute of
Engineering & Technology, Coimbatore .
• Actively attended a National level Conference on Computer & Communication System
Technology in Nehru Institute of Engineering & Technology, Coimbatore .
• Presented a paper & Debugging in KSR College of Engineering,Thiruchencode.
• Presented a paper & Technical quiz (Ist Prize) in Government college of
• Presented a paper & Debugging in PSNA college of Engineering & Technology,Dindigul.
• Active member in National level Technical Symposium “ELICTO 09” at Nehru Institute
of Engineering & Technology, Coimbatore
Class School/College Year of Passing Aggregate
B.E (ECE) Nehru Institute of Engineering & 2010 69
H.S.C Government boys higher secondary 2006 65
S.S.L.C Concordia higher secondary school. 2004 81
• Good grasping power and Technical Skills.
• Positive attitude and Enthusiastic in teamwork.
• Ability to handle crunch situations and adapt to any environment
Name : Sathiyamoorthy S
Father’s name : Saravanamoorthy
Date of Birth : 13 May 1989
Gender : Male
Hobbies : Watching movies and listening music.
Marital Status : Single
Languages Known : English,Tamil
Nationality : Indian
Address : Hno: 3/166c, Gundiyalnatham, Ankinayanapalli.(p.o),Krishnagiri
References will be provided on request. I hereby declare that the information given
Above is true & correct to the best of my knowledge.
Place: Hyderabad. (SATHIYAMOORHTY S)
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