Qinghui Wang

*** ******* **.

San Francisco, CA *4124

312-***-****

yrpa0h@r.postjobfree.com

OBJECTIVE

Seeking an entry level position in hardware, digital IC, ASIC or network company.

Current in OPT status

Available to work for any US employer

EDUCATION

M.S. in Electric Engineering, Illinois Institute Of Technology, Chicago, Illinois U.S. 05/2010

Concentration: VLSI and hardware design

B.S. in Communication Engineering, Jilin University, Changchun, Jilin, China. 07/2007

Concentration: WirelessCommunication, Satellite Communication

B.S. in Business Administration, Jilin University, Changchun, Jilin, China. 07/2007

SCHOLARSHIP and AWARDS

Second –class scholarship JLU 2007

First-class scholarship JLU 2006

First-class scholarship JLU 2005

Second-class scholarship JLU 2004

QUALIFICATIONS

2 years professional work experience at ASUS(PEGATRON) Technology Services Inc. as Hardware Engineer.

1 year professional work experience at Heilongjiang Communications Administration, Harbin, Heilongjiang, China as Network Engineer.

2+ years academic experience in Verilog HDL, VHDL and assembly language programming

4+ years academic experience in Wired and Wireless Networking(WLAN, Ethernet,802.11, BT, Cellular)

Hands on experience of embedded processors and supporting components.

Strong academic background on RF/amplifier/baseband design.

Current working experience on board level design.

Basic programming skill, C , java, C++.

Familiar with communication and modulation concepts including PSK, OFDM, QAM, etc.

TECHNICAL SKILLS

EDA: Matlab, OrCAD, Cadence, ISE, SUE, MicroSim, Protel.

Programming skill: Verilog HDL, C, C++, java,

Operating System: Mac OS X, Linux, Solaris, Windows XP/Vista/7 and Windows Server

Network: GSM,GDMA, LTE, VoIP, Wi-Fi, TCP/IP and WCDMA

PROJECT EXPERIENCE

-Logic design for Toshiba Thrive multi-dock with HDMI for 10.1-Inch Tablet; Pegatron 03/2011

-32-bit pipelined CPU in 0.5µm Technology Design; IIT 05/2009

Implemented a 32-bit pipelined CPU architecture using 0.5µm technology and synthesized by Synopsys tools. The maximum running frequency was 110MHz under synthesis; moreover, the design used booth encoded and Wallace tree structure in the multiplier block. Improved previous CPU’s specification, replaced multiplier with MAC block, optimized the 32-bit CPU with enhanced pipeline architecture. Improved the CPU’s maximum frequency about 40%, and only increased chip area less than 4% comparing to original one without pipeline.

-Power Control compensation system design for the Rain Attenuation in the Ku Band Satellite Communication System. JLU 06/2007

PROFESSIONAL EXPERIENCE

Hardware Engineer; ASUS(PEGATRON) Technology Services Inc. Jeffersonville, IN 05/2010-present

Collect the information of the RMA of ASUS laptop and desktop motherboards.

Failure analysis on the ASUS motherboards according the layout, and make reports on the certain products for the future improvement.

Support Sr. Electrical Engineer to design the new version product with ORCAD.

PCB Layout review and made advice.

Test new product before marketing and find defects.

Network Engineer; Heilongjiang Communications Administration, Harbin, Heilongjiang, China 07/2007-07/2008

Design GSM, CDMA, VOIP networks.

Maintain the network systems including servers, routers, and security system.

Control and monitor networks flows.

Install and modify networks equipment.

LANGUAGE

English

Mandarin

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